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MC141585 bảng dữ liệu(PDF) 11 Page - Motorola, Inc

tên linh kiện MC141585
Giải thích chi tiết về linh kiện  LCD Monitor On-Screen Display II - 16 (LMOSD2-16) CMOS
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

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MC141585
11
MOTOROLA
Window 3 Registers
Row 15 Coln 6
Row 15 Coln 7
Bit 2
WEN - It enables the window 3 generation if this bit
is set.
Bit 1
W_INT - This additional color related bit provides
the color intensity selection for window 3. Setting this bit to 0
means low intensity in this window and R,G,B output voltage
level equals to VDD(I). Set this bit to 1 will switch the supply
source of R,G,B back to VDD. Default setting is 0.
Bit 0
W_SHD - Shadowing on Window. Set this bit to
activate the window 3 shadowing.
Row 15 Coln 8
Bit 2-0 R, G and B - Controls the color of window 3.Refer
to Table 1 for color selection. Window 1 registers occupy Col-
umn 0-2 of Row 15, Window 2 from Column 3-5, Window 3
from 6-8 and Window 4 from 9-11. Window 1 has the highest
priority, and Window 4 the least. If window over-lapping
occurs, the higher priority window will cover the lower one, and
the higher priority color will take over on the overlap window
area. If the start address is greater than the end address, this
window will not be displayed.
Window 4 Registers
Row 15 Coln 9
Row 15 Coln 10
Bit 2
WEN - It enables the window 4 generation if this bit
is set.
0
1
2
3
4
5
6
7
ROW END ADDR
MSB
LSB
ROW START ADDR
MSB
LSB
COLN 6
ROW 15
COLN 7
ROW 15
WEN
W_INT
COL START ADDR
MSB
LSB
0
1
2
3
4
5
6
7
W_SHD
RG
COL END ADDR
MSB
LSB
COLN 8
0
1
2
3
4
5
6
7
B
ROW 15
0
1
2
3
4
5
6
7
ROW END ADDR
MSB
LSB
ROW START ADDR
MSB
LSB
COLN 9
ROW 15
WEN W_INT
COL START ADDR
MSB
LSB
COLN 10
0
1
2
3
4
5
6
7
ROW 15
W_SHD
Bit 1
W_INT - This additional color related bit provides
the color intensity selection for window 4. Setting this bit to 0
means low intensity in this window and R,G,B output voltage
level will be equal to VDD(I). Set this bit to 1 will switch the
supply source of R,G,B back to VDD. Default setting is 0.
Bit 0
W_SHD - Shadowing on Window. Set this bit to
activate the window 4 shadowing.
Row 15 Coln 11
Bit 2-0 R, G and B - Controls the color of window 4.Refer
to Table 1 for color selection. Window 1 registers occupy
Column 0-2 of Row 15, Window 2 from Column 3-5, Window
3 from 6-8 and Window 4 from 9-11. Window 1 has the high-
est priority, and Window 4 the least. If window over-lapping
occurs, the higher priority window will cover the lower one,
and the higher priority color will take over on the overlap win-
dow area. If the start address is greater than the end
address, this window will not be displayed.
Vertical Delay Control Register Row 15 Coln 12
Bit 7-0 VERTD - These 8 bits define the vertical starting
position. Total 256 steps, with an increment of four horizontal
lines per step for each field. Its value can’t be zero anytime.
The default value of it is 4.
Horizontal Delay Control Register Row 15 Coln 13
Bit 7-0 HORD - Horizontal starting position for character
display. 8 bits give a total of 256 steps and each increment
represents 5 or 6 dots(10x18 or 12x18 font) movement shift
to the right on the monitor screen. The movement of each
step is base on half character size. The default value is 15.
Character Height Control Register Row 15 Coln 14
Bit 7
X - Don’t care.
Bit 6
Reserved. Set to 0 for normal operation.
Bit 5-0
CH5-CH0 - This six bits will determine the dis-
played character height. LMOSD2
adopts 12 by 18 font
matrix and the middle 16 lines, line 2 to line 17, are
expanded by BRM algorithm. The top line and bottom line
will be duplicated dependent on the value of CH. No any line
is duplicated for top and bottom if CH is less than 32. One
extra duplicated line will be inserted for top and bottom if CH
RG
COL END ADDR
MSB
LSB
COLN 11
0
1
2
3
4
5
6
7
B
ROW 15
0
1
2
3
4
5
6
7
LSB
ROW 15
MSB
VERTD
COLN 12
0
1
2
3
4
5
6
7
LSB
ROW 15
MSB
HORD
COLN 13
7
ROW 15
6
54
32
1
0
CH5 CH4
CH3
CH2
CH1
CH0
COLN 14
X
0


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