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3 / 20 page Preliminary 3 64Mb SDRAM Ascend Semiconductor Corporation Features • Fully synchronous to positive clock edge • Single 3.3V +/- 0.3V power supply • LVTTL compatible with multiplexed address • Industrial temperature available • Programmable Burst Length ( BL ) - 1,2,4,8 or full page • Programmable CAS Latency ( CL ) -1, 2 or 3 • Data Mask ( DQM ) for Read/Write masking • Programmable wrap sequential - Sequential ( BL = 1/2/4/8/full page ) - Interleave ( BL = 1/2/4/8 ) • Burst read with single-bit write operation • All inputs are sampled at the positive rising edge of the system clock. • Auto refresh and self refresh • 4,096 refresh cycles / 64ms Ordering Information Description The AD484M1644VTA is Synchronous Dynamic Random Access Memory ( SDRAM ) organized as 1,048,756 words x 4 banks x 16 bits. All inputs and outputs are synchronized with the positive edge of the clock . The 64Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate in 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL . 64Mb( 4Banks ) Synchronous DRAM AD484M1644VTA ( 4Mx16 ) * Ascend Semiconductor reserves the right to change products or specification without notice. CL1 Note Low power Low power Low power Standard Standard Standard Standard Power Commercial Range : 0℃ ~ 70℃ Commercial Range : 0℃ ~ 70℃ Commercial Range : 0℃ ~ 70℃ Commercial Range : 0℃ ~ 70℃ Commercial Range : 0℃ ~ 70℃ Commercial Range : 0℃ ~ 70℃ Commercial Range : 0℃ ~ 70℃ Operation Range 54pins, TSOPII 54pins, TSOPII 54pins, TSOPII 54pins, TSOPII 54pins, TSOPII 54pins, TSOPII 54pins, TSOPII Package 100MHz 125MHz 143MHz 66MHz 143MHz 167MHz 183MHz Max Freg. AD484M1644VTA-10L AD484M1644VTA-8L AD484M1644VTA-7L AD484M1644VTA-15 AD484M1644VTA-7 AD484M1644VTA-6 AD484M1644VTA-55 Part number |
Số phần tương tự - AD484M1644VTA-10I |
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Mô tả tương tự - AD484M1644VTA-10I |
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