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ADC674AKP bảng dữ liệu(PDF) 6 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation.
tên linh kiện ADC674AKP
Giải thích chi tiết về linh kiện  Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER
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ADC674AKP bảng dữ liệu(HTML) 6 Page - Burr-Brown (TI)

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6
®
ADC674A
NOTE: Specifications are at + 25
°C and measured at 50% level of transitions.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
Convert Mode
tDSC
STS Delay from CE
60
200
ns
tHEC
CE Pulse Width
50
30
ns
tSSC
CS to CE Setup
50
20
ns
tHSC
CS Low During CE High
50
20
ns
tSRC
R/C to CE Setup
50
0
ns
tHRC
R/C Low During CE High
50
20
ns
tSAC
AO To CE Setup
0
ns
tHAC
AO Valid During CE high
50
20
ns
tC
Conversion Time, 12 Bit Cycle
9
12
15
µs
8 Bit Cycle
6
8
10
µs
Read Mode
tDD
Access Time From CE
75
150
ns
tHD
Data Valid After CE Low
25
35
ns
tHL
Output Float Delay
100
150
ns
tSSR
CS to CE Setup
50
0
ns
tSRR
R/C to CE Setup
0
ns
tSAR
AO to CE Setup
50
25
ns
tHSR
CS Valid After CE Low
0
ns
tHRR
R/C high After CE Low
0
ns
tHAR
AO Valid After CE Low
50
ns
tHS
STS delay After Data Valid
100
300
600
ns
TABLE IV. Timing Specifications
The STATUS output indicates the current state of the con-
verter by being in a high state only during conversion.
During this time the three state output buffers remain in a
high-impedance state, and therefore data cannot be read
during conversion. During this period additional transitions
of the three digital inputs which control conversion will be
ignored, so that conversion cannot be prematurely termi-
nated or restarted. However, if A
O changes state after the
beginning of conversion, any additional start conversion
transition will latch the new state of A
O, possibly resulting
in an incorrect conversion length (8 bits vs 12 bits) for that
conversion.
READING OUTPUT DATA
After conversion is initiated, the output data buffers remain
in a high-impedance state until the following four logic
conditions are simultaneously met: R/C high, STATUS low,
CE high, and CS low. Upon satisfaction of these conditions
the data lines are enabled according to the state of inputs
12/8 and AO. See Figure 4 and Table IV for timing relation-
ships and specifications.
FIGURE 4. Read Cycle Timing.
CE
t
SSR
CS
A
O
Data Valid
DB11-DB0
High-Z
STATUS
R/C
t
SRR
t
SAR
t
DD
t
HS
t
HL
t
HD
t
HAR
t
HRR
t
HSR
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.


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