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TMP102-Q1 bảng dữ liệu(PDF) 5 Page - Texas Instruments

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tên linh kiện TMP102-Q1
Giải thích chi tiết về linh kiện  TMP102-Q1 Low-Power Digital Temperature Sensor With SMBus and Two-Wire Serial Interface in SOT563
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TMP102-Q1 bảng dữ liệu(HTML) 5 Page - Texas Instruments

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TMP102-Q1
www.ti.com
SBOS702C – OCTOBER 2014 – REVISED DECEMBER 2015
6.6 Timing Requirements
see the Timing Diagrams section for additional information
HIGH-SPEED
FAST MODE
MODE
UNIT
MIN
MAX
MIN
MAX
ƒ(SCL)
SCL operating frequency
V+
0.001
0.4
0.001
2.85
MHz
Bus-free time between STOP and START
t(BUF)
600
160
ns
condition
Hold time after repeated START condition.
t(HDSTA)
600
160
ns
After this period, the first clock is generated.
See Two-Wire Timing Diagrams.
t(SUSTA)
repeated start condition setup time
600
160
ns
t(SUSTO)
STOP Condition Setup Time
600
160
ns
t(HDDAT)
Data hold time
100
900
25
105
ns
t(SUDAT)
Data setup time
100
25
ns
V+ , see Two-Wire Timing
t(LOW)
SCL-clock low period
1300
210
ns
Diagrams
t(HIGH)
SCL-clock high period
See Two-Wire Timing Diagrams
600
60
ns
tFD
Data fall time
See Two-Wire Timing Diagrams
300
80
ns
See Two-Wire Timing Diagrams
300
ns
tRD
Data rise time
SCLK
≤ 100 kHz, see Two-Wire
1000
ns
Timing Diagrams
tFC
Clock fall time
See Two-Wire Timing Diagrams
300
40
ns
tRC
Clock rise time
See Two-Wire Timing Diagrams
300
40
ns
Copyright © 2014–2015, Texas Instruments Incorporated
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