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TMP175 bảng dữ liệu(PDF) 6 Page - Texas Instruments |
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TMP175 bảng dữ liệu(HTML) 6 Page - Texas Instruments |
6 / 31 page TMP175-Q1, TMP75-Q1 SBOS759 – NOVEMBER 2015 www.ti.com 6.6 Timing Requirements see the Timing Diagrams and Two-Wire Timing Diagrams sections for additional information (1) HIGH-SPEED FAST MODE MODE UNIT MIN MAX MIN MAX ƒ(SCL) SCL operating frequency V+ 0.001 0.4 0.001 2.38 MHz Bus-free time between STOP and START t(BUF) 1300 160 ns condition Hold time after repeated START condition. t(HDSTA) 600 160 ns After this period, the first clock is generated. See the Timing Diagrams section t(SUSTA) Repeated START condition setup time 600 160 ns t(SUSTO) STOP condition setup time 600 160 ns t(HDDAT) Data hold time 4 900 4 120 ns t(SUDAT) Data setup time 100 10 ns t(LOW) SCL clock low period V+ , see the Timing Diagrams section 1300 280 ns t(HIGH) SCL clock high period See the Timing Diagrams section 600 60 ns tFD Data fall time See the Timing Diagrams section 300 150 ns See the Two-Wire Timing Diagrams section 300 40 ns tRC Clock rise time SCLK ≤ 100 kHz, see the Timing Diagrams 1000 ns section tFC Clock fall time See the Two-Wire Timing Diagrams section 300 40 ns (1) Values are based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not specified and are not production tested. 6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TMP175-Q1 TMP75-Q1 |
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Mô tả tương tự - TMP175 |
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