công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

ACE9030M bảng dữ liệu(PDF) 11 Page - Mitel Networks Corporation

tên linh kiện ACE9030M
Giải thích chi tiết về linh kiện  Radio Interface and Twin Synthesiser
Download  39 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  MITEL [Mitel Networks Corporation]
Trang chủ  http://www.mitel.com
Logo MITEL - Mitel Networks Corporation

ACE9030M bảng dữ liệu(HTML) 11 Page - Mitel Networks Corporation

Back Button ACE9030M Datasheet HTML 7Page - Mitel Networks Corporation ACE9030M Datasheet HTML 8Page - Mitel Networks Corporation ACE9030M Datasheet HTML 9Page - Mitel Networks Corporation ACE9030M Datasheet HTML 10Page - Mitel Networks Corporation ACE9030M Datasheet HTML 11Page - Mitel Networks Corporation ACE9030M Datasheet HTML 12Page - Mitel Networks Corporation ACE9030M Datasheet HTML 13Page - Mitel Networks Corporation ACE9030M Datasheet HTML 14Page - Mitel Networks Corporation ACE9030M Datasheet HTML 15Page - Mitel Networks Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 39 page
background image
ACE9030
11
FUNCTIONAL DESCRIPTION - CONTROL BUS
The functions of the ACE9030 fall into two separate
groups, the Radio Interface and the Synthesisers.
The common control bus splits the input strings differ-
ently for these two sections so this bus operation is described
first as an introduction to the available features.
All functions are controlled by a serial bus; DATA is a bi-
directional data line, to input all control data and to output the
results of measurements in the Radio Interface section, CL is
the clock, and LATCHB and LATCHC are the latch signals at
the end of each control word for either the Radio Interface or
the Synthesiser section respectively.
CL is a continuously running clock at typically 1·008 MHz,
and all incoming and output data are latched on rising edges
of this clock. The controller should clock data in and out on
falling clock edges. For bus control purposes the frequency of
CL may be widely varied and this clock does not need to be
continuous, however, the sampled I.F. signal AFCOUT, the
Polling ADC, and the Lock Detect Filter also use CL as the
sampling clock. In systems where any of these are required
the clock CL is constrained to be 1·008 MHz and to be
continuous.
To ensure clean initialisation the clock CL should give at
least 8 cycles before the power-up command and similarly to
set the control logic to known states there should be 8 cycles
of CL after a power-down command.
During normal operation there should be at least 30
cycles of CL between latch pulses, 24 for the data bits (see
figures 9,10 & 11) plus 6 extra. This minimum becomes 36
cycles if the extended synthesiser programming command
(A2) is used.
Radio Interface Bus - Receive
Fig.9 Radio Interface receive bus timing
The received data is split into three bytes, where DATA1
normally contains a value to be loaded into a destination set
by DATA2 and DATA3. When a command does not need to
put any information into byte DATA1 a preamble xx1010xx is
recommended to fill this byte. It is possible to set-up several
features in one bus operation and to allow this the decoding
only acts on single or selected bits; the others are given as “x”
in the block descriptions. Two bits of DATA2 also set the type
of command, with four options:
DATA2
DATA2
Type of
Comment
bit 7
bit 6
Command
0
0
SLEEP
No reply
0
1
NORMAL
Send requested data
1
0
SET-UP
No reply
1
1
TEST
No reply
and the CLK8 output driver will be active, and are used to clock
the microcontroller. To reduce the supply current to its mini-
mum in Sleep the synthesisers must also be powered down,
by a Word D message with DA and DM both set HIGH as
described under Synthesiser Bus - Receive Only. During
Sleep all set-up values are retained unless changed by a Set-
up command. The exit from Sleep is by any Normal command.
Normal commands will end Sleep mode but are primarily
used to change the operating mode of the cellular terminal or
to request ADC data. The ACE9030 will output data onto the
serial bus after a Normal command.
Set-up commands are used to adjust various operating
parameters but can also initiate a logic restart if DATA3 bits 1
and 0 are both “1” so for routine changes of set-ups these bits
should always be 00.
Test mode is included only for use during chip manufac-
ture.
Sleep mode is selected to put the cellular terminal into a
very low power state for when it is “Off” and neither waiting for,
nor setting up a call. In Sleep only the crystal and 8·064 MHz
oscillators, DAC1 and DAC2, the OSC8 phase locked loop,
The Sleep Command - DATA2 bits 7, 6 = 00
DATA1
DATA2
DATA3
xx1010xx
00xxxxxx
xxxxxxxx
CL
DATA
LATCHB
DATA1
DATA2
DATA3
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0


Số phần tương tự - ACE9030M

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
logo
ACE Technology Co., LTD...
ACE9006M ACE-ACE9006M Datasheet
492Kb / 7P
   N-Channel 60-V (D-S) MOSFET
VER 1.1
ACE9006M03N ACE-ACE9006M03N Datasheet
718Kb / 7P
   N-Channel 60-V MOSFET
VER 1.1
ACE9006M06P ACE-ACE9006M06P Datasheet
712Kb / 7P
   P-Channel 60-V MOSFET
VER 1.1
logo
Mitel Networks Corporat...
ACE9020 MITEL-ACE9020 Datasheet
187Kb / 7P
   Receiver and Transmitter Interface
logo
Zarlink Semiconductor I...
ACE9020 ZARLINK-ACE9020 Datasheet
417Kb / 6P
   Receiver and Transmitter Interface
More results

Mô tả tương tự - ACE9030M

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
logo
Zarlink Semiconductor I...
NJ8820 ZARLINK-NJ8820 Datasheet
493Kb / 11P
   FREQUENCY SYNTHESISER (PROM INTERFACE)
NJ88C25 ZARLINK-NJ88C25 Datasheet
197Kb / 8P
   FREQUENCY SYNTHESISER (MICROPROCESSOR SERIAL INTERFACE)
NJ88C21 ZARLINK-NJ88C21 Datasheet
476Kb / 8P
   FREQUENCY SYNTHESISER (MICROPROCESSOR INTERFACE) WITH RESETTABLE COUNTERS
NJ8821 ZARLINK-NJ8821 Datasheet
475Kb / 10P
   FREQUENCY SYNTHESISER (MICROPROCESSOR INTERFACE) WITH RESETTABLE COUNTERS
logo
General Electric Compan...
NJ8821 GEC-NJ8821 Datasheet
136Kb / 5P
   FREQUENCY SYNTHESISER (MICROPROCESSOR INTERFACE) WITH RESETTABLE COUNTERS
logo
Zarlink Semiconductor I...
ZIF600 ZARLINK-ZIF600 Datasheet
229Kb / 9P
   Pager Synthesiser and 4FSK Demodulator
NJ88C30 ZARLINK-NJ88C30 Datasheet
217Kb / 9P
   VHF SYNTHESISER
logo
List of Unclassifed Man...
TWC-78-1 ETC2-TWC-78-1 Datasheet
124Kb / 1P
   CABLE, RADIO FREQUENCY, TWIN CONDUCTOR, BALANCED LINE
logo
PMC-Sierra, Inc
PM7830 PMC-PM7830 Datasheet
123Kb / 2P
   Baseband Radio Interface Controller
logo
Zarlink Semiconductor I...
SP8858 ZARLINK-SP8858 Datasheet
547Kb / 21P
   1쨌5GHz Professional Synthesiser
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39


bảng dữ liệu tải về

Go To PDF Page


Link URL




Chính sách bảo mật
ALLDATASHEET.VN
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com