SM5166AV datasheet(9/11 Pages) NPC

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SM5166AV

NIPPON PRECISION CIRCUITS—9

Boost-up Signal

If the PLL momentarily loses lock as a result of a

phase error, a level signal is output on pin DB. When

the PLL is operating in lock, output DB goes high

impedance.

When the PLL starts up, the signal on DB charges

the low-pass ﬁlter capacitor in anticipation of high-

speed locking. After the boost-up signal is output and

the PLL phase error comes within tolerance, the

boost-up circuit stops and operation continues when

the 2 supplies (VDD1, VDD2) are applied and OPR

goes HIGH once only. After the boost-up circuit

stops, new data is written and the boost-up signal is

not output even if the VCO is not in lock.

Operating principles

When the PLL is operating with a phase error within

ﬁxed tolerance, an internal WINDOWN signal is

generated, as shown in ﬁgure 6. This signal is in sync

with the N counter output signal (FV) and is 64

cycles of the FIN input period in length centered

about the falling edge of FV.

If the phase detector error correction signal occurs

before the WINDOWN LOW-level pulsewidth, the

HIGH-level output from DB continues. However, if

the error correction signal occurs wholly within the

WINDOWN LOW-level pulsewidth, DB goes high

impedance and the boost-up circuit operation stops.

The above description applies when the error

correction signal is revising up. When the error

correction signal is revising down, DB goes LOW.

Standby Mode

The SM5166AV enters standby mode when OPR

goes LOW. In this mode, the states and functions

shown in table 2 occur.

In standby mode, some current ﬂows into VDD1

(FIN and XIN prescaler current). Therefore, it is

necessary to reduce VDD1 to 0 V to fully reduce

current consumption and reduce power dissipation.

Figure 6. boost-up signal timing

FR

FV

Phase Detector

error correction signal

WINDOWN

DB

∗∗

∗

Hi-Impedance

HIGH level output

: 32fFIN

∗

()

Table 2. Standby mode block states

Block

State

DO and DB

Floating (high impedance)

LD

LOW-level output

Phase

comparator

Reset

Input FIN

Feedback resistor is cutoff (HIGH level)

Input XIN

Feedback resistor is cutoff (HIGH level)

N counter

Reset

R counter

Reset

Latch data

Stored (while VDD2 is within rating)

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