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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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LM43602-Q1 bảng dữ liệu(PDF) 3 Page - Texas Instruments |
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LM43602-Q1 bảng dữ liệu(HTML) 3 Page - Texas Instruments |
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3 / 43 page  SW VIN PGND CBOOT VCC BIAS SYNC RT PGOOD EN SS/TRK AGND FB SW PGND VIN PAD 1 16 2 3 4 5 6 8 7 9 15 14 13 12 11 10 LM43602-Q1 www.ti.com SNVSA83A – APRIL 2015 – REVISED MAY 2015 6 Pin Configuration and Functions PWP Package 16-Pin HTSSOP Top View Pin Functions PIN TYPE(1) DESCRIPTION NAME NUMBER Switching output of the regulator. Internally connected to both power MOSFETs. Connect to SW 1,2 P power inductor. Boot-strap capacitor connection for high-side driver. Connect a high quality 470 nF capacitor CBOOT 3 P from CBOOT to SW. Internal bias supply output for bypassing. Connect bypass capacitor from this pin to AGND. VCC 4 P Do not connect external loading to this pin. Never short this pin to ground during operation. Optional internal LDO supply input. To improve efficiency, it is recommended to tie to VOUT when 3.3 V ≤ VOUT ≤ 28 V, or tie to an external 3.3 V or 5 V rail if available. When used, place BIAS 5 P a bypass capacitor (1 to 10 µF) from this pin to ground. Tie to ground when not in use. BIAS pin voltage should not exceed VIN. Clock input to synchronize switching action to an external clock. Use proper high speed SYNC 6 A termination to prevent ringing. Connect to ground if not used. Connect a resistor RT from this pin to AGND to program switching frequency. Leave floating RT 7 A for 500 kHz default switching frequency. Open drain output for power-good flag. Use a 10 k Ω to 100 kΩ pull-up resistor to logic rail or PGOOD 8 A other DC voltage no higher than 12 V. Feedback sense input pin. Connect to the midpoint of feedback divider to set VOUT. Do not FB 9 A short this pin to ground during operation. Analog ground pin. Ground reference for internal references and logic. Connect to system AGND 10 G ground. Soft-start control pin. Leave floating for internal soft-start slew rate. Connect to a capacitor to SS/TRK 11 A extend soft start time. Connect to external voltage ramp for tracking. Enable input to the internal LDO and regulator. High = ON and low = OFF. Connect to VIN, or EN 12 A to VIN through resistor divider,or to an external voltage or logic source. Do not float. Supply input pins to internal LDO and high side power FET. Connect to power supply and VIN 13,14 P bypass capacitors CIN. Path from VIN pin to high frequency bypass CIN and PGND must be as short as possible. Power ground pins, connected internally to the low side power FET. Connect to system PGND 15,16 G ground, PAD, AGND, ground pins of CIN and COUT. Path to CIN must be as short as possible. Low impedance connection to AGND. Connect to PGND on PCB. Major heat dissipation path PAD 17 — of the die. Must be used for heat sinking to ground plane on PCB. (1) P = Power, G = Ground, A = Analog Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM43602-Q1 |
Số phần tương tự - LM43602-Q1_15 |
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Mô tả tương tự - LM43602-Q1_15 |
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