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LM26003 bảng dữ liệu(PDF) 11 Page - Texas Instruments |
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LM26003 bảng dữ liệu(HTML) 11 Page - Texas Instruments |
11 / 32 page Iss x tss 1.236V Css = Vout 10 mV/Div VSW 5V/Div IL 200 mA/Div 1 2s/DIV LM26003, LM26003-Q1 www.ti.com SNVS576F – AUGUST 2008 – REVISED FEBRUARY 2015 8.3 Feature Description 8.3.1 FPWM Pulling the FPWM pin high disables sleep mode and forces the LM26003 device to always operate in PWM mode. Light load efficiency is reduced in PWM mode, but switching frequency remains stable. The FPWM pin can be connected to the VDD pin to pull it high. In FPWM mode, under light load conditions, the regulator operates in discontinuous conduction mode (DCM). In discontinuous conduction mode, current through the inductor starts at zero and ramps-up to its peak, then ramps-down to zero again. Until the next cycle, the inductor current remains at zero. At nominal load currents, in FPWM mode, the device operates in continuous conduction mode, where positive current always flows in the inductor. Typical discontinuous operation waveforms are shown in Figure 11. Figure 11. Discontinuous Mode Waveforms 75-mA Load, Vin = 12 V At very light load, in FPWM mode, the LM26003 device may enter sleep mode. This is to prevent an overvoltage condition from occurring. However, the FPWM sleep threshold is much lower than in normal operation. 8.3.2 Soft-Start The soft-start feature provides a controlled output voltage ramp-up at startup. This reduces inrush current and eliminates output overshoot at turn-on. The soft-start pin, SS, must be connected to GND through a capacitor. At power-on, enable, or UVLO recovery, an internal 2.5-µA (typical) current charges the soft-start capacitor. During soft-start, the error amplifier output voltage is controlled by both the soft-start voltage and the feedback loop. As the SS pin voltage ramps-up, the duty-cycle increases proportional to the soft-start ramp, causing the output voltage to ramp-up. The rate at which the duty-cycle increases depends on the capacitance of the soft-start capacitor. The higher the capacitance, the slower the output voltage ramps-up. The soft-start capacitor value can be calculated with the following equation: where • tss is the desired soft-start time • Iss is the soft-start source current. (1) During soft-start, current limit and synchronization remain in effect, while sleep mode and frequency foldback are disabled. Soft-start mode ends when the SS pin voltage reaches 1.23 V typical. At this point, output voltage control is transferred to the FB pin and the SS pin is discharged. 8.3.3 Current Limit The peak current limit is set internally by directly measuring peak inductor current through the internal switch. To ensure accurate current sensing, AVIN should be bypassed with a minimum 100-nF ceramic capacitor as close as possible to AVIN and GND pins. Also the PVIN pin should be bypassed with at least 2.2 µF to ensure low jitter operation. When the inductor current reaches the current limit threshold, the internal FET turns off immediately allowing inductor current to ramp-down until the next cycle. This reduction in duty-cycle corresponds to a reduction in output voltage. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LM26003 LM26003-Q1 |
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Mô tả tương tự - LM26003 |
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