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LM26001B bảng dữ liệu(PDF) 2 Page - Texas Instruments |
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LM26001B bảng dữ liệu(HTML) 2 Page - Texas Instruments |
2 / 27 page Exposed Pad Connect to GND GND 8 VIN 1 VIN 2 PGOOD 3 EN 4 SS 5 COMP 6 FB 7 9 FREQ 10 FPWM 11 SYNC 12 VBIAS 13 VDD 14 BOOT 15 SW 16 SW LM26001B SNVS491B – MAY 2007 – REVISED APRIL 2013 www.ti.com Connection Diagram Top View Figure 1. 16-Lead Exposed Pad HTSSOP Package See Package Number PWP0016A Pin Descriptions Pin # Pin Name Description 1 VIN Power supply input 2 VIN Power supply input 3 PGOOD Power Good pin. An open drain output which goes high when the output voltage is greater than 92% of nominal. 4 EN Enable is an analog level input pin. When pulled below 0.8V, the device enters shutdown mode. 5 SS Soft-start pin. Connect a capacitor from this pin to GND to set the soft-start time. 6 COMP Compensation pin. Connect to a resistor capacitor pair to compensate the control loop. 7 FB Feedback pin. Connect to a resistor divider between Vout and GND to set output voltage. 8 GND Ground 9 FREQ Frequency adjust pin. Connect a resistor from this pin to GND to set the operating frequency. 10 FPWM FPWM is a logic level input pin. For normal operation, connect to GND. When pulled high, sleep mode operation is disabled. 11 SYNC Frequency synchronization pin. Connect to an external clock signal for synchronized operation. SYNC must be pulled low for non-synchronized operation. 12 VBIAS Connect to an external 3V or greater supply to bypass the internal regulator for improved efficiency. If not used, VBIAS should be tied to GND. 13 VDD The output of the internal regulator. Bypass with a minimum 1.0 µF capacitor. 14 BOOT Bootstrap capacitor pin. Connect a 0.1µF minimum ceramic capacitor from this pin to SW to generate the gate drive bootstrap voltage. 15 SW Switch pin. The source of the internal N-channel switch. 16 SW Switch pin. The source of the internal N-channel switch. EP EP Exposed Pad thermal connection. Connect to GND. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM26001B |
Số phần tương tự - LM26001B_15 |
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Mô tả tương tự - LM26001B_15 |
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