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UVLO

VIN

2

3

LM25018

LM25018

www.ti.com

SNVS953D – DECEMBER 2012 – REVISED DECEMBER 2014

Feature Description (continued)

7.3.9 Undervoltage Detector

The LM25018 device contains a dual-level undervoltage lockout (UVLO) circuit. A summary of threshold voltages

and operational states is provided in Device Functional Modes. When the UVLO pin voltage is below 0.66 V, the

controller is in a low current shutdown mode. When the UVLO pin voltage is greater than 0.66 V but less than

used to set the minimum operating voltage of the regulator.

UVLO hysteresis is accomplished with an internal 20-

μA current source that is switched on or off into the

impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to

quickly raise the voltage at the UVLO pin. The hysteresis is equal to the value of this current times the resistance

satisfied.

Figure 11. UVLO Resistor Setting

7.3.10 Thermal Protection

The LM25018 device should be operated so the junction temperature does not exceed 150°C during normal

operation. An internal Thermal Shutdown circuit is provided to protect the LM25018 in the event of a higher than

normal junction temperature. When activated, typically at 165°C, the controller is forced into a low power reset

regulator is enabled, and normal operation is resumed.

7.3.11 Ripple Configuration

LM25018 uses constant on-time (COT) control scheme, in which the on-time is terminated by an on-timer, and

stable operation, the feedback voltage must decrease monotonically, in phase with the inductor current during

suppress any noise component present at the feedback node.

Table 1 shows three different methods for generating appropriate voltage ripple at the feedback node. Type 1

and Type 2 ripple circuits couple the ripple at the output of the converter to the feedback node (FB). The output

voltage ripple has two components:

1. Capacitive ripple caused by the inductor current ripple charging/discharging the output capacitor.

2. Resistive ripple caused by the inductor current ripple flowing through the ESR of the output capacitor.

The capacitive ripple is not in phase with the inductor current. As a result, the capacitive ripple does not

decrease monotonically during the off-time. The resistive ripple is in phase with the inductor current and

decreases monotonically during the off-time. The resistive ripple must exceed the capacitive ripple at the output

converters, with multiple on-time bursts in close succession followed by a long off-time.

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