LM20333

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SNVS558D – MAY 2008 – REVISED APRIL 2013

CURRENT LIMIT

The precise current limit enables the device to operate with smaller inductors that have lower saturation currents.

When the peak inductor current reaches the current limit threshold, an over current event is triggered and the

internal high-side FET turns off and the low-side FET turns on, allowing the inductor current to ramp down until

the next switching cycle. For each sequential over-current event, the reference voltage is decremented and PWM

pulses are skipped resulting in a current limit that does not aggressively fold back for brief over-current events,

while at the same time providing frequency and voltage foldback protection during hard short circuit conditions.

SOFT-START AND VOLTAGE TRACKING

The SS/TRK pin is a dual function pin that can be used to set the startup time or track an external voltage

source. The startup or soft-start time can be adjusted by connecting a capacitor from the SS/TRK pin to ground.

The soft-start feature allows the regulator output to gradually reach the steady state operating point, thus

reducing stresses on the input supply and controlling startup current. If no soft-start capacitor is used the device

defaults to the internal soft-start circuitry resulting in a startup time of approximately 1 ms. For applications that

require a monotonic startup or utilize the PGOOD pin, an external soft-start capacitor is recommended. The

SS/TRK pin can also be set to track an external voltage source. The tracking behavior can be adjusted by two

external resistors connected to the SS/TRK pin as shown in Figure 30 in the design guide.

PRE-BIAS STARTUP CAPABILITY

The LM20333 is in a pre-biased state when it starts up with an output voltage greater than zero. This often

occurs in many multi-rail applications such as when powering an FPGA, ASIC, or DSP. In these applications the

output can be pre-biased through parasitic conduction paths from one supply rail to another. Even though the

LM20333 is a synchronous converter, it will not pull the output low when a pre-bias condition exists. During start

up the LM20333 will not sink current until the soft-start voltage exceeds the voltage on the FB pin. Since the

device cannot sink current, it protects the load from damage that might otherwise occur if current is conducted

through the parasitic paths of the load.

POWER GOOD AND OVER VOLTAGE FAULT HANDLING

The LM20333 has built in under and over voltage comparators that control the power switches. Whenever there

is an excursion in output voltage above the set OVP threshold, the part will terminate the present on-pulse, turn-

on the low-side FET, and pull the PGOOD pin low. The low-side FET will remain on until either the FB voltage

falls back into regulation or the negative current limit is triggered which in turn tri-states the FETs. If the output

reaches the UVP threshold the part will continue switching and the PGOOD pin will be deasserted and go low.

Typical values for the PGOOD resistor are on the order of 100 k

Ω or less. To avoid false tripping during transient

glitches the PGOOD pin has 20 µs of built in deglitch time to both rising and falling edges.

UVLO

The LM20333 has an internal under-voltage lockout protection circuit that keeps the device from switching until

the input voltage reaches 4.25V (typical). The UVLO threshold has 350 mV of hysteresis that keeps the device

from responding to power-on glitches during start up. If desired the turn-on point of the supply can be changed

design guide.

THERMAL PROTECTION

Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum

junction temperature is exceeded. When activated, typically at 170°C, the LM20333 tri-states the power FETs

and resets soft-start. After the junction cools to approximately 150°C, the part starts up using the normal start up

routine. This feature is provided to prevent catastrophic failures from accidental device overheating.

Copyright © 2008–2013, Texas Instruments Incorporated

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