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LM20125 bảng dữ liệu(PDF) 11 Page - Texas Instruments |
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LM20125 bảng dữ liệu(HTML) 11 Page - Texas Instruments |
11 / 28 page IBOUNDARY = (VIN ± VOUT) x D 2 x L x fSW LM20125 www.ti.com SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 POWER GOOD AND OVER VOLTAGE FAULT HANDLING The LM20125 has built in under and over voltage comparators that control the power switches. Whenever there is an excursion in output voltage above the set OVP threshold, the part will terminate the present on-pulse, turn- on the low side FET, and pull the PGOOD pin low. The low side FET will remain on until either the FB voltage falls back into regulation or the zero cross detection is triggered which in turn tri-states the FETs. If the output reaches the UVP threshold the part will continue switching and the PGOOD pin will be asserted and go low. Typical values for the PGOOD resistor are on the order of 100 k Ω or less. To avoid false tripping during transient glitches the PGOOD pin has 16 µs of built in deglitch time to both rising and falling edges. UVLO The LM20125 has a built-in under-voltage lockout protection circuit that keeps the device from switching until the input voltage reaches 2.7V (typical). The UVLO threshold has 45 mV of hysteresis that keeps the device from responding to power-on glitches during start up. If desired the turn-on point of the supply can be changed by using the precision enable pin and a resistor divider network connected to VIN as shown in Figure 29 in the design guide. THERMAL PROTECTION Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated, typically at 160°C, the LM20125 tri-states the power FETs and resets Soft-Start. After the junction cools to approximately 150°C, the part starts up using the normal start up routine. This feature is provided to prevent catastrophic failures from accidental device overheating. LIGHT LOAD OPERATION The LM20125 offers increased efficiency when operating at light loads. Whenever the load current is reduced to a point where the peak to peak inductor ripple current is greater than two times the load current, the part will enter the diode emulation mode preventing significant negative inductor current. The point at which this occurs is the critical conduction boundary and can be calculated by the following equation: (1) Several diagrams are shown in Figure 24 illustrating continuous conduction mode (CCM), discontinuous conduction mode, and the boundary condition. It can be seen that in diode emulation mode, whenever the inductor current reaches zero the SW node will become high impedance. Ringing will occur on this pin as a result of the LC tank circuit formed by the inductor and the parasitic capacitance at the node. If this ringing is of concern an additional RC snubber circuit can be added from the switch node to ground. At very light loads, usually below 100 mA, several pulses may be skipped in between switching cycles, effectively reducing the switching frequency and further improving light-load efficiency. Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LM20125 |
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