LM2657

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SNVS342B – JANUARY 2005 – REVISED MARCH 2013

PIN DESCRIPTION (continued)

Pin 3, COMP1:

Compensation pin for Channel 1. This is the output of the error amplifier. The voltage level on this pin is compared with

an internally generated ramp signal to set the duty cycle for normal regulation. Since the Feedback pin is the inverting

input of the same error amplifier, the appropriate control loop compensation components are placed between this pin and

the Feedback pin. The COMP pin is internally pulled low during Soft-start to limit the duty cycle. Once Soft-start is

completed, the voltage on this pin can take up the value required to maintain output regulation. Note that an internal

voltage clamp does not allow the pin to go much higher than the steady-state requirement. This forms the ‘adaptive duty

cycle clamp’ circuit, which serves to limit the maximum allowable duty cycle and peak currents under sudden overloads.

Also note that this clamp has been designed with enough ‘headroom’ to permit an adequate response to step loads

within normal operating range.

Pin 4, SS1:

Channel 1 Soft-start pin. A Soft-start capacitor is placed between this pin and ground. A typical capacitance of 0.1µF is

recommended. During startup using chip Enable/power-up, soft-start is reset by connecting an internal 1.8 k

Ω resistor

charge on the Soft-start capacitors to ensure that the voltage on both Soft-start pins is below 100mV. Reset having thus

been obtained, an 11µA current source at this pin charges up the Soft-start capacitor. The voltage on this pin controls the

maximum duty cycle, and this produces a gradual ramp-up of the output voltage, thereby preventing large inrush currents

UVLO this pin is connected to an internal 115µA current sink whenever a current limit event is in progress. This sink

current quickly discharges the Soft-start capacitor and forces the duty cycle low to protect the power components.

Pin 5, VDD:

5V supply rail for the control and logic sections of both channels. For normal operation to start, the voltage on this pin

must be brought above 4.5V. Subsequently, the voltage on this pin (including any ripple component) should not be

allowed to fall below 4V for a duration longer than 7µs. Since this pin is also the supply rail for the internal control

sections, it should be well-decoupled particularly at high frequencies. A minimum 0.1µF-0.47µF (ceramic) capacitor

should be placed on the component side very close to the IC with no intervening vias between this capacitor and the

OFF. ‘Power Not Good’ is also signaled immediately (on Pin 9.) Normal operation will resume once the fault condition

has cleared. Additionally if the voltage on this pin falls below the minimum voltage required for logic operation (about

1.8V typ) the part will shutdown identically to enable (see pin 8) being pulled low.

Pin 6, FREQ:

Frequency adjust pin. The switching frequency (for both channels) is set by a resistor connected between this pin and

ground. A value of 22.1k

Ω sets the frequency to 300kHz (nominal). If the resistance is increased, the switching frequency

falls. An approximate relationship is that for every 7.3k

Ω increase (or decrease) in the value of the frequency adjust

resistance, the time period (1/f) increases (or decreases) by about 1µs.

Pin 7, SGND:

Signal Ground pin. This is the lower rail for the control and logic sections of both channels. SGND should be connected

on the PCB to the system ground, which in turn is connected to PGND1 and PGND2. The layout is important and the

recommendations in the section LAYOUT GUIDELINES should be followed.

Pin 8, EN:

IC Enable pin. When EN is taken high, both channels are enabled by means of a Soft-start power-up sequence (see Pin

4). When EN is brought low, ‘Power Not Good’ is signaled within 100ns. The Soft-start capacitor is then discharged by an

internal 1.8k

Pin 9, PGOOD:

Power Good output pin. An open-Drain logic output that is pulled high with an external pull-up resistor, indicating that

enable is high. Outside this window, this pin is internally pulled low (‘Power Not Good’ signaled) provided the output error

first before fault monitoring becomes active (i.e. PGOOD must have been high prior to occurrence of the fault condition

for a fault to be asserted). For correct signaling on this pin under single-channel operation, see description of Pin 2.

Pin 10, FPWM:

Logic input for selecting either the Forced PWM (‘FPWM’) Mode or Pulse-skip Mode (‘SKIP’) for both channels (together).

When the pin is driven high, the IC operates in the FPWM mode, and when pulled low or left floating, the SKIP mode is

enabled. In FPWM mode, the lower FET of a given channel is always ON whenever the upper FET is OFF (except for a

narrow shoot-through protection deadband). This leads to continuous conduction mode of operation, which has a fixed

frequency and (almost) fixed duty cycle down to very light loads. But this does reduce efficiency at light loads. The

alternative is the SKIP mode, where the lower FET remains ON only till the voltage on the Switch pin (see Pin 27 or Pin

16) goes above -2.2mV (typical). So for example, for a 21m

Ω FET, this translates to a current threshold of 2.2/21 = 0.1A.

Therefore if the (instantaneous) inductor current falls below this value, the lower FET will turn OFF every cycle at this

point (when operated in SKIP mode). This threshold is set by the ‘Zero-cross Comparator’ in the Block Diagram. Note

that if the inductor current waveform is high enough to cause the SW pin to be always below this ‘zero-cross threshold’

(see ELECTRICAL CHARACTERISTICS table), there will be no observable difference between FPWM and SKIP mode

settings (in steady-state). SKIP mode, when it occurs, is clearly a discontinuous mode of operation. However, in

conventional discontinuous mode, the duty cycle keeps falling (towards zero) as the load decreases. But the LM2657

does not ‘allow’ the duty cycle to fall by more than 15% of its original value (at the CCM-DCM boundary). This leads to

pulse-skipping, and so the average frequency decreases as the load decreases. This mode of operation improves

efficiency at light loads, but the frequency is effectively no longer a constant. Note that a minimum preload of 0.1mA

should be maintained on the output of each channel to ensure regulation in SKIP mode. The resistive divider from output

to ground used to set the output voltage could be designed to serve as this preload.

Pin 11, SS2:

Soft-start pin for Channel 2. See Pin 4.

Pin 12, COMP2: Compensation pin for Channel 2. See Pin 3.

Pin 13, FB2:

Feedback pin for Channel 2. See Pin 2.

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