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SM59A16U1 bảng dữ liệu(PDF) 4 Page - SyncMOS Technologies,Inc

tên linh kiện SM59A16U1
Giải thích chi tiết về linh kiện  Instruction-set compatible with MCS-51
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nhà sản xuất  SYNCMOS [SyncMOS Technologies,Inc]
Trang chủ  http://www.syncmos.com.tw
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SM59A16U1 bảng dữ liệu(HTML) 4 Page - SyncMOS Technologies,Inc

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SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071
Ver A SM59A16U1 04/12/2013
- 4 -
17.1
Low Voltage Control Register( LVC ) ....................................................................................................113
18.
10-bit Analog-to-Digital Converter ( ADC ).....................................................................................................114
18.1
ADC Control Register 1( ADCC1 )........................................................................................................114
18.2
ADC Control Register 2( ADCC2 )........................................................................................................115
18.3
ADC Data( ADCDH, ADCDL )...............................................................................................................115
18.4
ADC Clock Select( ADCCS ) ................................................................................................................116
19.
USB function ................................................................................................................................................117
19.1
USB Device Enumeration Transfer.......................................................................................................117
19.2
USB Interrupt In Transfer .....................................................................................................................117
19.3
USB Interrupt Out Transfer...................................................................................................................117
19.4
USB Bulk Transfer From Host to Device...............................................................................................118
19.5
USB Bulk Transfer From Device to Host ...............................................................................................118
19.6
USB Control 1 Register( UCTRL1 ) ..................................................................................................... 120
19.7
USB Control 2 Register( UCTRL2 ) .................................................................................................... 121
19.8
USB Status Register( USTAT ) ............................................................................................................ 121
19.9
USB Device Address Register( DEVADR ) .......................................................................................... 122
19.10
USB Frame Number Register( FRMNUMH, FRMNUML ) ................................................................ 122
19.11
USB Host Stall Register( HSTALL ) ................................................................................................. 122
19.12
USB Device Stall Register( DSTALL ).............................................................................................. 123
19.13
USB Handshake Status Register( HSKSTAT ) ................................................................................. 123
19.14
USB Interrupt Enable Register 1( UIER1 )....................................................................................... 125
19.15
USB Interrupt Enable Register 2( UIER2 )....................................................................................... 125
19.16
USB Interrupt Flag Register 1( UIFR1 ) ........................................................................................... 126
19.17
USB Interrupt Flag Register 2( UIFR2 ) ........................................................................................... 126
19.18
USB Endpoint Data Ready Register( EPDRDY ) ............................................................................. 127
19.19
USB Endpoint 0 Data Counter Register( EP0CNT )......................................................................... 128
19.20
USB Endpoint 1 Data Counter Register( EP1CNT )......................................................................... 128
19.21
USB Endpoint 2 Data Counter Register( EP2CNT )......................................................................... 128
19.22
USB Endpoint 3 Data Counter Register( EP3CNT )......................................................................... 128
19.23
USB Endpoint 4 Data Counter Register( EP4CNT )......................................................................... 129
19.24
USB Endpoint 0 Data Register( EP0DATA ).................................................................................... 129
19.25
USB Endpoint 1 Data Register( EP1DATA )..................................................................................... 129
19.26
USB Endpoint 2 Data Register( EP2DATA )..................................................................................... 129
19.27
USB Endpoint 3 Data Register( EP3DATA )..................................................................................... 130
19.28
USB Endpoint 4 Data Register( EP4DATA )..................................................................................... 130
20.
Barcode ...................................................................................................................................................... 131
20.1
Barcode Control Register( BCCTRL ) .................................................................................................. 131
20.2
Start Address to SRAM Register( ADDR2ML, ADDR2MH ) .................................................................. 132
20.3
Length of Data Register( LNGDATAL, LNGDATAH ) ............................................................................ 133
20.4
Rising of Data Register( RDATA ) ........................................................................................................ 133
20.5
Falling of Data Register( FDATA )........................................................................................................ 133
21.
In-System Programming ( Internal ISP )....................................................................................................... 134
21.1
ISP service program............................................................................................................................ 134
21.2
Lock Bit ( N )....................................................................................................................................... 134
21.3
Program the ISP Service Program....................................................................................................... 135
21.4
Initiate ISP Service Program ............................................................................................................... 135
21.5
ISP register
– TAKEY, IFCON, ISPFAH, ISPFAL, ISPFD and ISPFC.................................................... 136
21.6
Time Access Key Register( TAKEY ) ................................................................................................... 136
21.7
Interface Control Register( IFCON ) .................................................................................................... 137
21.8
ISP Flash Address Register( ISPFAH, ISPFAL ) .................................................................................. 137
21.9
ISP Flash Data Register( ISPFD ) ....................................................................................................... 137
21.10
ISP Flash Control Register( ISPFC ) ............................................................................................... 137
22.
OPA/Comparator ......................................................................................................................................... 139
22.1
Op/Comparator Pin Select( OpPin )..................................................................................................... 140
22.2
Op/Comparator Pin Select 2( OpPin2 )................................................................................................ 141
22.3
Comparator 0 Control( Cmp0CON ) .................................................................................................... 141


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