ISL267817

5

FN7877.2

April 19, 2012

REFERENCE INPUT

VREF

VREF Input Range

0.1

2.5

V

VREFLEAK Current Drain

-100

4

100

µA

-20

0.23

20

µA

CS/SHDN = +VCC

-3

0.01

3

µA

DIGITAL INPUT/OUTPUT

Logic Family

CMOS

Input High Voltage

3

+VCC + 0.3

V

Input Low Voltage

-0.3

0.8

V

Output High Voltage

3.5

V

Output Low Voltage

0.4

V

Output Coding

Two’s Complement

Input Leakage Current

-1

1

µA

Input Capacitance

10

pF

Floating-State Output Current

-1

1

µA

Floating-State Output Capacitance

5

pF

POWER REQUIREMENTS

Supply Voltage Range

4.75

5.25

V

Supply Current

430

800

µA

38

µA

223

µA

Power Down Current

0.5

3

µA

TEMPERATURE RANGE

Specified Performance

-40

+85

°C

NOTES:

6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

7. The absolute voltage applied to each analog input must be between GND and +VCC to guarantee datasheet performance.

9. See “Power vs Throughput Rate” on page 13 for more information regarding lower sample rates.

Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 6) TYP

MAX

(Note 6)

UNITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 6)

TYP

MAX

(Note 6)

UNITS

Analog Input Sample Time

1.5

2.0

Clk Cycles

Conversion Time

12

Clk Cycles

Throughput Rate

200

kHz

CS/SHDN Falling Edge to DCLOCK Low

0

ns

CS/SHDN Falling Edge to DCLOCK Rising Edge

30

ns

DCLOCK Falling Edge to Current DOUT Not Valid

15

ns