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ISL26104AV28EV1Z bảng dữ liệu(PDF) 11 Page - Intersil Corporation |
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ISL26104AV28EV1Z bảng dữ liệu(HTML) 11 Page - Intersil Corporation |
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11 / 21 page  ISL26102, ISL26104 11 FN7608.0 October 12, 2012 case, there is no difference in power consumption for standby or power-down modes. The Output Word Rate register allows the user to set the rate at which the converter performs conversions. Table 3 lists the output word rate options. The Input Mux Selection register defines the input signal that will be used when conversions are performed. The signals include either 2 (ISL26102) or 4 (ISL26104) differential input channels, an on-chip temperature sensor, or the monitor node for the AVDD supply voltage. Note that if the temperature sensor or the AVDD monitor are selected the PGA gain is internally set for 1x gain. The PGA Gain register allows the user to set the PGA gain setting for the channel pointed to by the Channel Pointer register. The PGA provides gain settings of 1x (in this gain setting the programmable gain amplifier is actually bypassed and the signal goes directly to the modulator), 2x, 4x, 8x, 16x, 32x, 64x, and 128x. The Conversion Control register provides the means to initiate offset calibration, or initiate single or continuous conversions. If bit b2 of this register is set to a logic 1, an offset calibration will be performed and the states of bits b1 and b0 are ignored. The state of bit b2 will be set back to a logic 0 after the offset calibration is complete. If the b1b0 bits are set to 01, a single conversion will be performed. When the conversion is completed, the bits will be set back to 00, the SDO/RDY pin will be taken low (note that the CS pin must be a logic 1 for SDO/RDY to fall) and the conversion data will be held in a register. If the user enables CS (held at logic 1) and provides 24 SCLKs to the SCLK pin, the data word will be shifted out of the SDO/RDY pin as a 24-bit two’s complement word, starting with the MSB. Data bits are clocked out on the rising edge of SCLK. If the entire 24-bit data word is not read before the completion of the next conversion, it will be overwritten with the new conversion word. If the b1b0 bits are set to 10, conversions will be performed continuously until bits b1b0 are set to either 00 or 01, Standby mode is activated, or the PDWN pin is taken low. Refer to “Reading Conversion Data” on page 14. The Delay Timer register allows the user to program a delay time, which will be inserted between the time that the user selects an input to be converted via the Input Mux Selection register and when the conversion is started. If continuous conversions are selected via the Conversion Control register, the Input Mux Selection register can be changed without needing to stop conversions. The Delay Timer register allows the user to insert a delay between when the mux is changed and when a new conversion is started. If the Delay Timer register is set to all 0's the minimum delay will be 100µs. Any time the PGA Gain setting is changed, the channel selection is changed, or a command is given to start conversion(s), the user can expect a delay before the SDO/RDY signal will fall. This delay is defined by Equation 1: The first 4ms is for the PGA to settle. This delay cannot be changed. The Delay Timer register setting is user controllable, and it dictates the majority of the second section of the equation. The 4*(1/OWR) term is the time required for the filter to settle at the OWR (Output Word Rate), which has been selected in the Output Word Rate register. The PGA Offset Array registers hold the calibration results for the offset calibration done for each of the PGA gain settings. The result of an offset calibration is a 24-bit twos complement word. There are eight high byte registers, eight mid byte registers and eight low byte registers. When reading or writing to one of the PGA Offset Array byte registers, the register selected will be determined by the PGA Pointer Register. The PGA Pointer register contains the pointer to the PGA Offset register array bytes associated with a specific PGA gain. 4ms Delay Timer Register Setting∗4ms () 100μs ) 4∗ 1OWR ⁄ () ++ + [] (EQ. 1) |
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