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ISL22317WFRTZ bảng dữ liệu(PDF) 5 Page - Intersil Corporation

tên linh kiện ISL22317WFRTZ
Giải thích chi tiết về linh kiện  Low Noise, Low Power, I2C??Bus, 128 Taps
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nhà sản xuất  INTERSIL [Intersil Corporation]
Trang chủ  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL22317WFRTZ bảng dữ liệu(HTML) 5 Page - Intersil Corporation

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5
FN6912.1
April 15, 2010
tD
Power-up Delay
VCC above Vpor, to DCP Initial Value
Register recall completed, and I2C Interface
in standby state
1ms
EEPROM SPECIFICATION
EEPROM Endurance
1,000,000
Cycles
EEPROM Retention
Temperature T
≤ +55°C50
Years
Temperature T
≤ +125°C15
Years
tWC
(Note 21)
Non-volatile Write Cycle Time
12
20
ms
SERIAL INTERFACE SPECS
VIL
A1, A0, SDA, and SCL Input Buffer
LOW Voltage
0.3*VCC
V
VIH
A1, A0, SDA, and SCL Input Buffer
HIGH Voltage
0.7*VCC
V
Hysteresis
(Note 19)
SDA and SCL Input Buffer Hysteresis
0.05*VCC
V
VOL
(Note 19)
SDA Output Buffer LOW Voltage,
Sinking 4mA
00.4
V
Cpin
(Note 19)
A1, A0, SDA, and SCL Pin
Capacitance
10
pF
fSCL
SCL Frequency
400
kHz
tsp
Pulse Width Suppression Time at SDA
and SCL Inputs
Any pulse narrower than the max spec is
suppressed
50
ns
tAA
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of VCC, until
SDA exits the 30% to 70% of VCC window
900
ns
tBUF
Time the Bus must be Free Before the
Start of a New Transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC
during the following START condition
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
100
ns
tHD:DAT
Input Data Hold Time
From SCL falling edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
0ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC,
to SDA rising edge crossing 30% of VCC
600
ns
tHD:STO
STOP Condition Hold Time for Read,
or Volatile Only Write
From SDA rising edge to SCL falling edge;
both crossing 70% of VCC
1300
ns
tDH
Output Data Hold Time
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC
window
0ns
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 22)
TYP
(Note 7)
MAX
(Note 22)
UNIT
ISL22317


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