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ISL24211IRTZ-EVALZ bảng dữ liệu(HTML) 8 Page - Intersil Corporation

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ISL24211
8
FN7585.0
February 23, 2011
By finding the difference of Equation 13 and Equation 12, the total
span of VCOM can be found:
Assuming that the IDVROUT(MIN) = 0 instead of ISTEP, the
expression in Equation 14 simplifies to:
DVR_OUT Pin Leakage Current
When the voltage on the DVR_OUT pin is greater than 10V, an
additional leakage current flows into the pin in addition to the
ISET current. Figure 6 shows the ISET current and the DVR_OUT
pin current for DVR_OUT pin voltage up to 19V. In applications
where the voltage on the DVR_OUT pin will be greater than 10V,
the actual output voltage will be lower than the voltage
calculated by Equation 8. The graph in Figure 6 was measured
with RSET = 4.99kΩ.
Power Supply Sequence
The recommended power supply sequencing is shown in
Figure 7. When applying power, VDD should be applied before or
at the same time as AVDD. The minimum time for tVS is 0µs.
When removing power, the sequence of VDD and AVDD is not
important.
Do not remove VDD or AVDD within 100ms of the start of the
EEPROM programming cycle. Removing power before the
EEPROM programming cycle is completed may result in
corrupted data in the EEPROM.
Operating and Programming
Supply Voltage and Current
To program the EEPROM, AVDD must be ≥10.8V. If programming
is not required, the ISL24211 will operate over an AVDD range of
4.5V to 19V.
During EEPROM programming, IDD and IAVDD will temporarily be
higher than their quiescent currents. Figure 8 shows a typical IDD
and IAVDD current profile during EEPROM programming. The
current pulses are Erase and Write cycles. The EEPROM
programming algorithm is shown in Figure 9. The algorithm
attempts up to 4 erase cycles and 4 programming cycles,
however typical parts only require 1 cycle of each, sometimes 2
when AVDD is near the minimum 10.8V limit.
VCOMSPAN
AVDD
R2
R1 R2
+
--------------------
⎝⎠
⎜⎟
⎛⎞
1
1
256
----------
⎝⎠
⎛⎞
R1
20RSET
--------------------
⎝⎠
⎜⎟
⎛⎞
=
(EQ. 14)
VCOMSPAN
R1 R
2
R1 R2
+
--------------------
⎝⎠
⎜⎟
⎛⎞ AVDD
20RSET
--------------------
⎝⎠
⎜⎟
⎛⎞
R1 R
2
R1 R2
+
--------------------
⎝⎠
⎜⎟
⎛⎞
IDVROUT MAX
()
==
(EQ. 15)
FIGURE 6. DVR_OUT PIN LEAKAGE CURRENT
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0
2
4
6
8
10
12
14
16
18
20
OUT PIN VOLTAGE (V)
OUT PIN CURRENT
SET PIN CURRENT
REGISTER = 255
VDD
AVDD
tVS
FIGURE 7. POWER SUPPLY SEQUENCE
~1ms
IP
100ms
Max
2.7mA
200µA
50µA
90µA
25µA
FIGURE 8. IDD AND IAVDD CURRENT PROFILE DURING EEPROM
PROGRAMMING


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