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ISL28022FRZ bảng dữ liệu(PDF) 7 Page - Intersil Corporation

tên linh kiện ISL28022FRZ
Giải thích chi tiết về linh kiện  Precision Digital Power Monitor
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ISL28022
7
FN8386.7
October 2, 2015
Submit Document Feedback
DC ACCURACY
ADC Resolution (Native)
PGA gain = /1, VSENSE = ±320mV
16
Bits
Current Measurement Error
TA = +25°C
±0.2
±0.3
%
Current Measurement Error
Over-temperature
TA = -40°C to +85°C
±0.5
%
TA = -40°C to +125°C
±1
%
Bus Voltage Measurement Error
TA = +25°C
±0.2
±0.3
%
Bus Voltage Measurement Error
Over-temperature
TA = -40°C to +85°C
±0.5
%
TA = -40°C to +125°C
±1
%
ADC TIMING SPECS
ts
ADC Conversion Time
Mode = 5 or 6
ADC setting = 0000
72
79.2
µs
ADC setting = 0001
132
145.2
µs
ADC setting = 0010
258
283.8
µs
ADC setting = 0011
508
558.8
µs
ADC setting = 1001
1.01
1.11
ms
ADC setting = 1010
2.01
2.21
ms
ADC setting = 1011
4.01
4.41
ms
ADC setting = 1100
8.01
8.81
ms
ADC setting = 1101
16.01
17.61
ms
ADC setting = 1110
32.01
35.21
ms
ADC setting = 1111
64.01
70.41
ms
I2C INTERFACE SPECIFICATIONS
VIL
SDA and SCL Input Buffer LOW Voltage
-0.3
0.3 x VCC
V
VIH
SDA and SCL Input Buffer HIGH Voltage
0.7 x VCC
VCC + 0.3
V
Hysteresis
SDA and SCL Input Buffer Hysteresis
0.05 x VCC
V
VOL
SDA Output Buffer LOW Voltage, Sinking
3mA
VCC = 5V, IOL = 3mA
0
0.02
0.4
V
CPIN
SDA and SCL Pin Capacitance
TA = +25°C, f = 1MHz,
VCC = 5V, VIN = 0V,
VOUT = 0V
10
pF
fSCL
SCL Frequency
400
kHz
tIN
Pulse Width Suppression Time at SDA
and SCL Inputs
Any pulse narrower than the max
spec is suppressed.
50
ns
tAA
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of VCC,
until SDA exits the 30% to 70% of VCC
window.
900
ns
tBUF
Time the Bus Must be Free Before the
Start of a New Transmission
SDA crossing 70% of VCC during a
STOP condition, to SDA crossing 70%
of VCC during the following START
condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge.
Both crossing 70% of VCC.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30%
of VCC to SCL falling edge crossing
70% of VCC.
600
ns
Electrical Specifications TA = +25°C, VCC = 3.3, VINP = VBUS = 12V, VSENSE = VINP-VINM = 32mV, unless otherwise specified. All
voltages with respect to GND pin. (Continued)
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
(Note 8)TYP
MAX
(Note 8)UNIT


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