 |
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
|
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
ADC12D1600CCMPR bảng dữ liệu(PDF) 4 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
ADC12D1600CCMPR bảng dữ liệu(HTML) 4 Page - Texas Instruments |
|
|
4 / 67 page  VA AGND VA AGND 100 VA AGND VA AGND 100 VBIAS 50k 50k 50k VA AGND VA AGND 50k Control from VCMO VCMO 100 ADC12D1600QML SNAS615 – DECMEBER 2012 www.ti.com Pin Descriptions and Equivalent Circuits Table 2. Analog Front-End and Clock Pins Pin No. Name Equivalent Circuit Description Differential signal I- and Q-inputs. In the Non-Dual Edge Sampling (Non-DES) Mode, each I- and Q-input is sampled and converted by its respective channel with each positive transition of the CLK input. In Non-ECM (Non-Extended Control Mode) and DES Mode, both channels sample the I- input. In Extended Control Mode (ECM), the Q-input may optionally be selected for conversion in DES Mode by the DEQ Bit (Addr: 0h, Bit 6). Each I- and Q-channel input has an internal common mode bias that is disabled when DC-coupled Mode is selected. Both H1/J1 VinI+/- inputs must be either AC- or DC-coupled. The coupling mode N1/M1 VinQ+/- is selected by the VCMO Pin. In Non-ECM, the full-scale range of these inputs is determined by the FSR Pin; both I- and Q-channels have the same full-scale input range. In ECM, the full-scale input range of the I- and Q-channel inputs may be independently set via the Control Register (Addr: 3h and Addr: Bh). Note that the high and low full-scale input range setting in Non-ECM corresponds to the mid and minimum full-scale input range in ECM. The input offset may also be adjusted in ECM. Differential Converter Sampling Clock. In the Non-DES Mode, the analog inputs are sampled on the positive transitions of U2/V1 CLK+/- this clock signal. In the DES Mode, the selected input is sampled on both transitions of this clock. This clock must be AC-coupled. Differential DCLK Reset. A positive pulse on this input is used to reset the DCLKI and DCLKQ outputs of two or more ADC12D1600s in order to synchronize them with other ADC12D1600s in the system. DCLKI and DCLKQ are always V2/W1 DCLK_RST+/- in phase with each other, unless one channel is powered down, and do not require a pulse from DCLK_RST to become synchronized. The pulse applied here must meet timing relationships with respect to the CLK input. Although supported, this feature has been superseded by AutoSync. 4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADC12D1600QML |
Số phần tương tự - ADC12D1600CCMPR |
|
Mô tả tương tự - ADC12D1600CCMPR |
|
|
Link URL |
| Chính sách bảo mật |
| ALLDATASHEET.VN |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
