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ADC12D1600QML bảng dữ liệu(PDF) 11 Page - Texas Instruments |
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ADC12D1600QML bảng dữ liệu(HTML) 11 Page - Texas Instruments |
11 / 67 page VDR DR GND + - + - ADC12D1600QML www.ti.com SNAS615 – DECMEBER 2012 Table 5. High-Speed Digital Output Pins (continued) Ball No. Name Equivalent Circuit Description A18/A19 DId11+/- B17/C16 DId10+/- A16/B16 DId9+/- B15/C15 DId8+/- C14/D14 DId7+/- A14/B14 DId6+/- B13/C13 DId5+/- C12/D12 DId4+/- Delayed I- and Q-channel Digital Data Outputs. In Non- A12/B12 DId3+/- Demux Mode, these outputs are tri-stated. In Demux Mode, B11/C11 DId2+/- these outputs provide ½ the data at ½ the sampling clock C10/D10 DId1+/- rate, synchronized with the non-delayed data, i.e. the other A10/B10 DId0+/- ½ of the data which was sampled one clock cycle later. · · Compared with the DI and DQ outputs, these outputs Y18/Y19 DQd11+/- represent the earlier time samples. If used, each of these W17/V16 DQd10+/- outputs should always be terminated with a 100 Ω differential Y16/W16 DQd9+/- resistor placed as closely as possible to the differential W15/V15 DQd8+/- receiver. V14/U14 DQd7+/- Y14/W14 DQd6+/- W13/V13 DQd5+/- V12/U12 DQd4+/- Y12/W12 DQd3+/- W11/V11 DQd2+/- V10/U10 DQd1+/- Y10/W10 DQd0+/- Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: ADC12D1600QML |
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