74FCT38072S datasheet(5/11 Pages) IDT

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REVISION A 03/18/15

5

LOW SKEW 1 TO 2 CLOCK BUFFER

74FCT38072S DATASHEET

AC Electrical Characteristics

(VDD = 1.8V, 2.5V, 3.3V)

VDD = 1.8V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise

VDD = 2.5 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise

VDD = 3.3 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise

Notes:

1. With rail to rail input clock

2. Between any 2 outputs with equal loading.

3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input Frequency

0200

MHz

Output Rise Time

tOR

0.36 to 1.44 V, CL=5 pF

0.6

1.0

ns

Output Fall Time

tOF

1.44 to 0.36 V, CL=5 pF

0.6

1.0

ns

Start-up Time

tSTART-UP

Part start-up time for valid outputs

after VDD ramp-up

2ms

Propagation Delay

Note 1

1.5

2.5

4

ns

Buffer Additive Phase Jitter, RMS

125MHz, Integration Range:

12kHz-20MHz

0.05

ps

Output to Output Skew

Rising edges at VDD/2, Note 2

50

65

ps

Device to Device Skew

Rising edges at VDD/2

200

ps

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input Frequency

0

200

MHz

Output Rise Time

tOR

0.5 to 2.0 V, CL=5 pF

0.6

1.0

ns

Output Fall Time

tOF

2.0 to 0.5 V, CL=5 pF

0.6

1.0

ns

Start-up Time

tSTART-UP

Part start-up time for valid outputs

after VDD ramp-up

2ms

Propagation Delay

Note 1

1.8

2.5

4.5

ns

Buffer Additive Phase Jitter, RMS

125MHz, Integration Range:

12kHz-20MHz

0.05

ps

Output to Output Skew

Rising edges at VDD/2, Note 2

50

65

ps

Device to Device Skew

Rising edges at VDD/2

200

ps

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input Frequency

0

200

MHz

Output Rise Time

tOR

0.66 to 2.64 V, CL=5 pF

0.6

1.0

ns

Output Fall Time

tOF

2.64 to 0.66 V, CL=5 pF

0.6

1.0

ns

Start-up Time

tSTART-UP

Part start-up time for valid outputs

after VDD ramp-up

2ms

Propagation Delay

Note 1

1.5

2.5

4

ns

Buffer Additive Phase Jitter, RMS

125MHz, Integration Range:

12kHz-20MHz

0.05

ps

Output to Output Skew

Rising edges at VDD/2, Note 2

50

65

ps

Device to Device Skew

Rising edges at VDD/2

200

ps

Số phần tương tự - 74FCT38072S

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