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STC5455 bảng dữ liệu(PDF) 8 Page - Connor-Winfield Corporation |
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STC5455 bảng dữ liệu(HTML) 8 Page - Connor-Winfield Corporation |
8 / 56 page Page 8 of 56 TM121 Rev:P1.3 Date: October 24, 2011 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice STC5455 Synchronous Clock for SETS Data sheet Preliminary Register Map Table 2: Register Map Addr Reg Name Bits Type Description 0x00 Chip_ID 15-0 R Chip ID = 0x5455 0x01 0x02 Chip_Rev 7-0 R Chip revision number 0x03 Chip_Sub_Rev 7-0 R Chip firmware revision number 0x07 Fill_Obs_Window 3-0 R/W Activity monitor: Leaky bucket fill observation window 0x08 Leak_Obs_Window 3-0 R/W Activity monitor: Leaky bucket leak observation window 0x09 Bucket_Size 5-0 R/W Activity monitor: Leaky bucket size 0x0A Assert_Threshold 5-0 R/W Activity monitor: Leaky bucket alarm assert threshold 0x0B De_Assert_Threshold 5-0 R/W Activity monitor: Leaky bucket alarm de-assert threshold 0x0C Freerun_Cali 10-0 R/W Freerun calibration, 2’s complement, -102.4 to +102.3ppm, step in 0.1ppm 0x0D 0x0E Disqualification_Range 9-0 R/W Reference disqualification range, 0 ~102.3ppm. The value is also specified as pull-in range 0x0F 0x10 Qualification_Range 9-0 R/W Reference qualification range, 0 ~102.3ppm. 0x11 0x12 Qualification_Soaking_Time 5-0 R/W Reference qualification soaking time, 0~63s 0x13 Ref_Index_Selector 3-0 R/W Select a reference input to access the register Ref_Info and Ref_Acceptable_Freq. 0x14 Ref_Info 15-0 R Frequency offset and frequency info of the reference selected by register Ref_Index_Selector 0x15 0x16 Ref_Activity 4 - 0 R Reference activity for reference 1 to 5 0x18 Ref_Qual 4 - 0 R Reference 1 ~ 5 qualification 0x1A Interrupt_Event_Status 7-0 R/W Status of interrupt events 0x1B Interrupt__Event_Enable 7-0 R/W Selects which of interrupt events will assert pin EVENT_INTR 0x1C Interrupt_Config 1-0 R/W Pin EVENT_INTR configuration and idle mode 0x1D Hard-wired_Switch_Pre_Selection 7-0 R/W Pre-selected reference number 1 and reference number 2 for hard- wired switch mode 0x1E SRCSW_States 0 R Indicates the states of pin SRCSW 0x1F 1 T0/T4_Tag_Select 0 R/W Selects registers between T0 and T4 for register 0x20 - 0x3F 0x20 Control_Mode 7,5-2 R/W Holdover history usage, Revertive, Manual/Auto, OOP, SRCSW 0x21 Loop_Bandwidth 7-0 R/W Loop bandwidth selection 0x22 Auto_Elect_Ref 3-0 R Indicates the reference elected by auto reference elector 0x23 Manual_Select_Ref 3-0 R/W The reference specified by users for manual selection mode 0x24 Selected_Ref 3-0 R Indicates the PLL current selected reference 0x25 Device_Holdover_History 31-0 R Device Holdover History 0x26 0x27 0x28 0x29 Long_Term_Accu_History 31-0 R Long term Accumulated History 0x2A 0x2B 0x2C |
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