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STC5425 bảng dữ liệu(PDF) 1 Page - Connor-Winfield Corporation |
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STC5425 bảng dữ liệu(HTML) 1 Page - Connor-Winfield Corporation |
1 / 48 page Page 1 of 48 TM113 Rev: P1.3 Date: September 20, 2011 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice STC5425 Line Card Clock Functional Specification Data sheet Preliminary Figure 1:Functional Block Diagram Description The RoHS 6/6 compliant STC5425 is a single chip clock synchronization solution for line card applica- tions in SDH, SONET, and Synchronous Ethernet network elements. The STC5425 accepts 5 clock reference inputs, 3 external frame sync inputs (EX_SYNC1, 2, 3) and generates 4 synchronized clock outputs. Synchro- nized outputs may be programmed for wide variety of frequencies from 1MHz up to 156.25MHz, in 1kHz steps. Reference inputs are individually monitored for activity and quality. Reference selection may be auto- matic, manual, or hard-wired manual. The timing generator may operate in the Freerun, Synchronized, and Holdover. It includes a DSP- based PLL. Synchronized mode is external timing while freerun and holdover mode are self-timing. DSP-based PLL technology removes any external component except the oscillator. It provides excellent performance and reliability to STC5425. The STC5425 is clocked by an external oscillator, either a stable TCXO or XO, as required by applica- tion. Features - Suitable for SONET, SDH, and Synchronous Ethernet applications - Supports 4 different frequencies of external oscillator upon soft-reset: 10MHz, 12.8MHz, 19.2MHz, 20MHz - Provides three 2kHz or 8kHz external frame sync input - Accepts 5 clock reference inputs - Supports automatically frequency detection or manually acceptable frequency. Each reference input is monitored for activity and quality - Automatic, manual, and hard-wired manual reference selection - Outputs 4 synchronized clock outputs, including 2 frame pulse clocks - Frequency translation of input clock to a different local line card clock - 3 clock synthesizers generate frequencies - Phase-align locking or hit-less reference switching - Programmable loop bandwidth, from 13Hz to 100Hz - Programmable phase skew in synthesizer level - SPI bus interface - Single 3.3V operation - IEEE 1149.1 JTAG boundary scan - Available in TQFP64 package 5 Synth F 8kHz 2kHz EX_SYNC 1 Timing SPI Interface CLK1, LVPECL/LVDS CLK8K Ref Monitor CLK2K 3 LVCMOS + 2 LVPECL/LVDS/LVCMOS TCXO Generator SRCSW Synthesizer G1 Ref Clk Synthesizer G4 CLK2 EX_SYNC 2 EX_SYNC 3 XO |
Số phần tương tự - STC5425 |
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Mô tả tương tự - STC5425 |
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