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STC5420 bảng dữ liệu(PDF) 1 Page - Connor-Winfield Corporation |
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STC5420 bảng dữ liệu(HTML) 1 Page - Connor-Winfield Corporation |
1 / 70 page Page 1 of 70 TM112 Rev: 2.0 Date: September 28, 2011 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice STC5420 Synchronous Clock for SETS Functional Specification Data sheet Description The RoHS 6/6 compliant STC5420 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2, G.8262 EEC Opt1 and Opt2 and Telcordia GR1244 and GR253. The STC5420 accepts 12 clock reference inputs and gener- ates 10 synchronized clock outputs: CLK1~CLK8, frame pulse clock CLK8K at 8kHz, and frame pulse clock CLK2K at 2kHz. CLK1~CLK8 may be programmed for wide variety of frequencies from 1MHz up to 156.25MHz, in 1kHz steps. Reference inputs are individually monitored for activity and quality. Reference selection may be automatic, manual, and hard-wired manual. Two independent timing generators, T0 and T4, may oper- ate in the Freerun, Synchronized, Pseudo Holdover, and Holdover mode. Each timing generator includes a DSP- based PLL. Synchronized mode external timing while fre- erun and holdover mode are self-timing. T0 supports Mas- ter/Slave and Multiple Master operation for redundant design. T4 only supports master operation. DSP-based PLL technology removes any external component except the oscillator. It provides excellent performance and reliability to STC5420. The STC5420 is clocked by an external oscillator (TCXO or OCXO). Using a well-chosen external oscillator ensures the STC5420 meet the required specification and standards. Features - Complies with ITU-T G.813 Opt1/Opt2, G.8262 EEC Opt1/Opt2, Telcordia GR1244 and GR253 (Stratum3/4E/ 4/SMC) - Two timing generators T0 and T4; T4 may lock to T0’s synchronized output - Supports Master/Slave and Multiple-Master redundant application (T0 timing generator only) - Provides programmable compensation for phase delay between master and slave unit, in 0.1ns steps - Accepts external oscillator at frequency of 10MHz, 12.8MHz, 19.2MHz,or 20MHz with programming - Accepts 12 clock reference inputs - Supports frequency auto detection or manually accept- able frequency for reference inputs. Each of them is monitored for activity and quality - Automatic/manual/hard-wired manual reference select - Outputs 10 synchronized clock outputs, including 2 frame pulse clocks CLK8K and CLK2K - 10 clock synthesizers generate frequencies - Programmable phase skew in synthesizer level - Phase-align or hit-less reference locking/switching - Programmable loop bandwidth, from 0.1Hz to 100Hz - Supports bus interface: Intel, Motorola, Multiplex, SPI - Single 3.3V operation - IEEE 1149.1 JTAG boundary scan - Available in TQFP100 package Figure 1:Functional Block Diagram 12 Synth F Frame8K Frame2K Composite EX_SYNC Master_Slave T0 Timing µ P Interface CLK1, LVPECL/LVDS CLK8K CLK3 Ref Monitor CLK2K 10 LVCMOS + 2 LVPECL/LVDS OCXO TCXO Generator T4 Timing Generator SRCSW Synthesizer G1 Ref Clk 2 Synthesizer G2 Synthesizer G3 Synthesizer G4 Synthesizer G5 Synthesizer G6 Synthesizer G7 Synthesizer G8 Synthesizer GT4 CLK2, LVPECL/LVDS CLK4 CLK5 CLK6 CLK7 CLK8 |
Số phần tương tự - STC5420 |
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Mô tả tương tự - STC5420 |
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