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SM3-ITG bảng dữ liệu(PDF) 7 Page - Connor-Winfield Corporation

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Giải thích chi tiết về linh kiện  ULTRA MINIATURE STRATUM 3 MODULE
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SM3-ITG bảng dữ liệu(HTML) 7 Page - Connor-Winfield Corporation

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SM3-ITG Data Sheet #:
TM074
Page 7 of 32 Rev: 05 Date: 09/06/11
© Copyright 2011 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Detailed Description continued
TheM/SOutputortheOutput1ofeachdevicemaybecross-connectedtotheotherdevice’sM/SRefinput.Thedeviceauto-
detectsthefrequencyontheM/SRefinput.MasterorslavestateofadeviceisdeterminedbytheM/Spin.Thus,master/slavestateis
alwaysmanuallycontrolledbytheapplication.Themastersynchronizestotheselectedinputreference,whiletheslavesynchronizes
totheM/SRefinput.(Notethat8kHzframephasealignmentismaintainedacrossamaster/slavepairofdevicesonlyifM/SOutputis
usedasthecrosscouplesignal.)
Theunitoperatinginslavemodelocksonandphase-alignstothecross-referenceclock(M/SOutputorOutput1)fromtheunit
inmastermode.Thephaseskewbetweentheinputcross-referenceandtheoutputclockfortheslaveunitistypicallylessthan±1ns
(under±3nsindynamicsituations,includingreferencejitterandwander).
PerfectphasealignmentofthetwoOutput1outputclockswouldrequirenodelayonthecross-referenceclockconnection.
Toaccommodatepathlengthdelays,theSM3-ITGprovidesaprogrammablephaseskewfeature.Theslave’sOutput1orM/S
Outputmaybephaseshifted-32nSto+31.75nSrelativetoM/SInputaccordingtothecontentsoftheMS_Phase_Offsetregisterto
compensateforthepathlengthoftheM/SOutputorOutput1toM/SInputconnection.Thisoffsetmaythereforebeprogrammedto
exactlycompensatefortheactualpathlengthdelayassociatedwiththeparticularapplication’scross-referencetraces.Theoffsetmay
furtherbeadjustedtoaccommodateanyoutputclockdistributionpathdelaydifferences.Thus,master/slaveswitcheswiththeSM3-
ITGdevicesmaybeaccomplishedwithnear-zerophasehits.
Thefirsttimeaunitbecomesaslave,suchasimmediatelyafterpower-up,itsoutputclockphasestartsoutarbitrary,andwill
quicklyphase-aligntothecross-referencefromthemasterunit.Thephaseskewwillbeeliminated(orconvergedtotheprogrammed
phaseoffset)stepbystep.Thewholepull-in-and-lockprocesswillcompleteinabout60seconds.Thereisnofrequencyslew
protectioninslavemode.Inslavemode,theunit’smissionistolocktoandfollowthemaster.
Onceapairofunitshasbeenoperatinginalignedmaster/slavemode,andamaster/slaveswitchoccurs,theunitthatbecomes
masterwillmaintainitsoutputclockphaseandfrequencywhileaphasebuild-out(tothecurrentoutputclockphase)isperformedon
itsselectedreferenceinput.Therefore,asmastermodeoperationcommences,therewillbenophaseorfrequencyhitsontheclock
output.
Likewise,theunitthatbecomestheslavewillmaintainitsoutputclockfrequencyandphasefor1msecbeforestartingtofollowthe
cross-reference,protectingthedownstreamclockusersduringtheswitch.Assumingthephaseoffsetisprogrammedfortheactual
propagationdelayofthiscross-referencepath,therewillagainbenophasehitsontheoutputclockoftheunitthathastransitioned
frommastertoslave.
Master / Slave Configuration
Figure 3
STC3500
SM3-ITG
M/S OUTPUT / OUTPUT1
M/S OUTPUT / OUTPUT1
M/S REF
REFS1-4
REFS1-4
M/S REF
2
SM3-ITG
1
Furthermore,underregisteraccesscontrol,abackupholdoverhistoryregisterisprovided.Itmaybeloadedfromtheactiveholdover
historyorrestoredtotheactiveholdoverhistory.Theactiveholdoverhistorymayalsobeflushed.
Holdovermodemaybeenteredatanytime.Ifthereisnoholdoverhistoryavailable,theprioroutputfrequencywillbemaintained.
Wheninholdover,theapplicationmayread(viaregisteraccess)thetimesinceholdoverwasenterred.
Master/Slave Operation
PairsofSM3-ITGdevicesmaybeoperatedinamaster/slaveconfigurationforredundanttimingsourceapplications.Atypical
configurationisshownbelow.:


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