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SM3E bảng dữ liệu(PDF) 6 Page - Connor-Winfield Corporation |
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SM3E bảng dữ liệu(HTML) 6 Page - Connor-Winfield Corporation |
6 / 36 page SM3E Data Sheet #: TM054 Page 6 of 36 Rev: 04 Date: 01/26/11 © Copyright 2011 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice TheSM3Eutilizesupto8externalreferences,eachfrom8kHzto77.76MHz,maybeequippedandmonitoredforsignalpresence andfrequencyoffset.Additionally,across-couple8kHzreferenceinputisprovidedformaster/slaveoperation.Referenceselection maybemanualorautomatic,accordingtopre-programmedpriorities.Allreferenceswitchesareperformedinahitlessmanner,and frequencyrampcontrolsensuresmoothoutputsignaltransitions.Whenreferencesareswitched,thedeviceprovidesacontrollable phasebuild-outtominimizephasetransitionsintheoutputclocks. Threeoutputsignalsareprovided,thefirstupto77.76MHz,thesecondfixedat8kHzforuseasaframesyncsignalaswellas across-couplereferenceformaster/slaveoperation.Inslavemode,theoutputphasemaybeadjustedfrom-32to+31.75nSrelative tothemaster,toaccommodatedownstreamsystemneeds,suchasdifferentclockdistributionpathlengths.ThethirdoutputisaBITS clock,selectableaseither1.544MHzor2.048MHz. DeviceoperationmaybeinFreeRun,locked,orHoldOvermodes.InFreeRun,theclockoutputsaresimplydeterminedbythe FreeRunfrequencyandaccuracyofthecalibratedinternalclock.Inlockedmode,thechipphaselockstotheselectedinputreference. Whilelocked,afrequencyhistoryisaccumulated.InHoldOvermode,thechipoutputsaregeneratedaccordingtothishistory. TheDigitalPhaseLockedLoopprovidescriticalfilteringandfrequency/phasecontrolfunctionsthatmeetorexceedall requirementsincriticaljitterandaccuracyperformanceparameters.Filterbandwidthmaybeconfiguredtosuitapplications requirements. ControlfunctionsareprovidedviastandardSPIbusregisterinterface.Registeraccessprovidesvisibilityintoavarietyofregistered informationaswellasprovidingextensiveprogrammablecontrolcapability. Operating Modes: The SM3E Operates in Either Free Run, Locked, or Hold Over Mode: Free Run–InFreeRunmode,Output 1, M/S_Out, and BITS_Clk,theoutputclocks,aredetermineddirectlyfromandhavethe accuracyofthecalibratedfreerunninginternalclock.Referenceinputscontinuetobemonitoredforsignalpresenceandfrequency offset,butarenotusedtosynchronizetheoutputs. Locked–TheOutput 1, M/S_Out, andBITS_Clk,outputsarephaselockedtoandtracktheselectedinputreference.Upon enteringtheLockedmode,thedevicebeginsanacquisitionprocessthatincludesreferencequalificationandfrequencyslewrate limiting,ifneeded.Oncesatisfactorylockisachieved,the“Locked”bitissetintheDPLL_Statusregister,andacompilationofthe frequencyhistoryoftheselectedreferenceisstarted.WhenausableHoldOverhistoryhasbeenestablished,the Hold_Goodpinis set,andthe“HoldOverAvailable”bitissetinthe DPLL_Statusregister. PhasecomparisonandphaselockloopfilteringoperationsintheSM3Earecompletelydigital.Asaresult,deviceandloop behaviorareentirelypredictable,repeatable,andextremelyaccurate.Carefullydesignedandprovenalgorithmsandtechniques ensurecompletelyhitlessreferenceswitches,operationalmodechanges,andmaster/slaveswitches. Basicloopbandwidthisprogrammablefrom0.84mHzto1.6Hertz,givingtheuserawiderangeofcontroloverthesystem response. Whenanewreferenceisacquired,maximumfrequencyslewlimitsensuresmoothfrequencychanges.Oncelockisachieved, (<700secondsforStratum3E),the“Locked”bitisset.IftheSM3Eisunabletomaintainlock,LossofLock (LOL)isasserted.All transitionsbetweenlocked,HoldOverandFreeRunmodesareperformedwithminimalphaseeventsandsmoothfrequencyand phasetransitions. Referencephasehitsorphasedifferencesencounteredwhenswitchingreferences(orwhenenteringlockedmode)arenulled outwithanautomaticphasebuild-outfunction.Phasebuild-outisperformedwitharesidualphaseerroroflessthan1nS,andcan optionallybedisabledforhitsontheselectedreference,asrequiredforStratum3E. Hold Over–UponenteringHoldOvermode,theOutput 1, M/S_Out, and BITS_Clk,outputsaredeterminedfromtheHoldOver historyestablishedforthelastselectedreference.OutputfrequencyisdeterminedbyaweightedaverageoftheHoldOverhistory,and accuracyisdeterminedbytheinternalclock.HoldOvermodemaybeenteredmanuallyorautomatically.AutomaticentryintoHold Overmodeoccurswhenoperatingintheautomaticmode,thereferenceislost,andnoothervalidreferenceexists.Thetransferinto andoutofHoldOvermodeisdesignedtobesmoothandfreeoftransients.Thefrequencyslewisalsolimitedtoamaximumof±2 ppm/sec. Thehistoryaccumulationalgorithmusesafirstorderfrequencydifferencefilteringalgorithm.Typicalholdoveraccumulationtakes about15minutes.Whenausableholdoverhistoryhasbeenestablished,the Hold_Good pinisset,andthe“HoldoverAvailable”bitis setinthe DPLL_Status register.Theholdoverhistorycontinuestobeupdatedafter“HoldoverAvaialble”isdeclared. ThealgorithmaccumulatestheholdoverhistoryonlywhenithaslockedoneitheranexternalreferenceinMasteroperationorthe M/S Ref clockinSlaveoperation,starting15minutesafterpowerup.Trackingwillbesuspendedautomaticallywhenswitchingtoa newreferenceandinFreeRunorHoldOvermode.Asetofregistersallowstheapplicationtocontrolaholdoverhistorymaintenance policy,enablingeitherare-buildorcontinuanceofthehistorywhenareferenceswitchoccurs. Detailed Description |
Số phần tương tự - SM3E_15 |
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Mô tả tương tự - SM3E_15 |
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