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74LV4094
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 19 December 2011
11 of 21
NXP Semiconductors
74LV4094
8-stage shift-and-store bus register
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9.
Propagation delay strobe input (STR) to output (QPn), strobe input (STR) pulse width and the clock
set-up and hold times for strobe input
tW
tPHL
tPLH
th
VI
GND
VOH
VOL
QPn output
STR input
VM
VM
001aaf114
tsu
VI
GND
CP input
VM
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 10. The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold times
001aaf115
GND
GND
th
tsu
th
tsu
VM
VM
VM
VI
VOH
VOL
VI
QPn, QS1, QS2 output
CP input
D input


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