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74LV4094 bảng dữ liệu(PDF) 8 Page - NXP Semiconductors

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74LV4094
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 19 December 2011
8 of 21
NXP Semiconductors
74LV4094
8-stage shift-and-store bus register
11. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol
Parameter
Conditions
40 C to 85 C
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
tpd
propagation
delay
CP to QS1; see Figure 8
[3]
VCC = 1.2 V
-
90
-
-
-
ns
VCC = 2.0 V
-
31
58
-
70
ns
VCC = 2.7 V
-
23
43
-
51
ns
VCC = 3.0 V to 3.6 V
[2]
-17
34
-
41
ns
VCC = 3.3 V; CL = 15 pF
-
14
-
-
-
ns
CP to QS2; see Figure 8
[3]
VCC = 1.2 V
-
80
-
-
-
ns
VCC = 2.0 V
-
27
51
-
61
ns
VCC = 2.7 V
-
20
38
-
45
ns
VCC = 3.0 V to 3.6 V
-
14
30
-
36
ns
VCC = 3.3 V; CL = 15 pF
[2]
-13
-
-
-
ns
CP to QPn; see Figure 8
[3]
VCC = 1.2 V
-
115
-
-
-
ns
VCC = 2.0 V
-
39
75
-
90
ns
VCC = 2.7 V
-
29
55
-
66
ns
VCC = 3.0 V to 3.6 V
[2]
-22
44
-
53
ns
VCC = 3.3 V; CL = 15 pF
-
18
-
-
-
ns
STR to QPn; see Figure 9
[3]
VCC = 1.2 V
-
105
-
-
-
ns
VCC = 2.0 V
-
36
68
-
82
ns
VCC = 2.7 V
-
26
50
-
60
ns
VCC = 3.0 V to 3.6 V
[2]
-20
40
-
48
ns
VCC = 3.3 V; CL = 15 pF
-
17
-
-
-
ns
ten
enable time
OE to QPn; see Figure 11
[4]
VCC = 1.2 V
-
100
-
-
-
ns
VCC = 2.0 V
-
34
65
-
77
ns
VCC = 2.7 V
-
25
48
-
56
ns
VCC = 3.0 V to 3.6 V
[2]
-19
38
-
45
ns
tdis
disable time
OE to QPn; see Figure 11
[5]
VCC = 1.2 V
-
65
-
-
-
ns
VCC = 2.0 V
-
24
40
-
49
ns
VCC = 2.7 V
-
18
32
-
37
ns
VCC = 3.0 V to 3.6 V
[2]
-14
26
-
30
ns


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