74ALVCH32973

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© NXP B.V. 2013. All rights reserved.

Product data sheet

Rev. 3 — 17 January 2013

11 of 17

NXP Semiconductors

74ALVCH32973

16-bit bus transceiver and transparant D-type latch; 8 buffers

Measurement points are given in Table 10.

Fig 7.

Propagation delay, input (Dn) to data output (Yn)

DDD

'QLQSXW

<QRXWSXW

*1'

Measurement points are given in Table 10.

Fig 8.

3-state enable and disable times

DDD

RXWSXWV

HQDEOHG

RXWSXWV

HQDEOHG

RXWSXWV

GLVDEOHG

RXWSXW

/2:WR2))

2))WR/2:

RXWSXW

+,*+WR2))

2))WR+,*+

Q72(Q/2( LQSXW

*1'

*1'

Measurement points are given in Table 10.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig 9.

Data setup and hold times for input (nAn) to input (nLE)

DDD

*1'

*1'

Q$Q LQSXW

Q/( LQSXW