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LF3320QC15 bảng dữ liệu(PDF) 4 Page - LOGIC Devices Incorporated |
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LF3320QC15 bảng dữ liệu(HTML) 4 Page - LOGIC Devices Incorporated |
4 / 24 page DEVICES INCORPORATED LF3320 Horizontal Digital Image Filter 2-4 08/16/2000–LDS.3320-N Video Imaging Products ROUT11-0 — Reverse Cascade Output In Single Filter Mode, ROUT11-0 is a 12-bit registered cascade output port. ROUT11-0 on one device should be connected to RIN11-0 of another LF3320. In Dual Filter Mode, ROUT3-0 is a 4-bit registered output port for the upper four bits of the 16-bit Filter B output. In this mode, ROUT11-4 is disabled. Controls LDA — Coefficient A Load When LDA is LOW, data on CFA11-0 is latched into the Filter A LF InterfaceTM on the rising edge of CLK. When LDA is HIGH, data is not loaded into the Filter A LF InterfaceTM. When enabling the LF InterfaceTM for data input, a HIGH to LOW transition of LDA is required in order for the input circuitry to function properly. Therefore, LDA must be set HIGHimmediatelyafterpowerupto ensure proper operation of the input circuitry (see the LF InterfaceTM section for a full discussion). CENA — Coefficient Address Enable A When CENA is LOW, data on CAA7-0 is latched into Coefficient Address Register A on the rising edge of CLK. When CENA is HIGH, data on CAA7-0 is not latched and the register’s contents will not be changed. LDB — Coefficient B Load When LDB is LOW, data on CFB11-0 is latched into the Filter B LF InterfaceTM on the rising edge of CLK. When LDB is HIGH, data is not loaded into the Filter B LF InterfaceTM. When enabling the LF InterfaceTM for data input, a HIGH to LOW transition of LDB is required in order for the input circuitry to function properly. Therefore, LDB must be set HIGHimmediatelyafterpowerupto ensure proper operation of the input circuitry (see the LF InterfaceTM section for a full discussion). CENB — Coefficient Address Enable B When CENB is LOW, data on CAB7-0 is latched into Coefficient Address Register B on the rising edge of CLK. When CENB is HIGH, data on CAB7-0 is not latched and the register’s contents will not be changed. TXFRA — Filter A LIFO Transfer Control TXFRA is used to change which LIFO in the data reversal circuitry sends data to the reverse data path and which LIFO receives data from the forward data path in Filter A. When TXFRA goes LOW, the LIFO sending data to the reverse data path becomes the LIFO receiving data from the forward data path, and the LIFO receiving data from the forward data path becomes the LIFO sending data to the reverse data path. The device must see a HIGH to LOW transition of TXFRA in order to switch LIFOs. TXFRA is latched on the rising edge of CLK. TXFRB — Filter B LIFO Transfer Control TXFRB is used to change which LIFO in the data reversal circuitry sends data to the reverse data path and which LIFO receives data from the forward data path in Filter B. When TXFRB goes LOW, the LIFO sending data to the reverse data path becomes the LIFO receiving data from the forward data path, and the LIFO receiving data from the forward data path becomes the LIFO sending data to the reverse data path. The device must see a HIGH to LOW transition of TXFRB in order to switch LIFOs. TXFRB is latched on the rising edge of CLK. ACCA — Accumulator A Control When ACCA is HIGH, Accumulator A is enabled for accumulation and the Accumulator A Output Register is disabled for loading. When ACCA is LOW, no accumulation is performed and the Accumulator A Output Register is enabled for loading. ACCA is latched on the rising edge of CLK. ACCB — Accumulator B Control When ACCB is HIGH, Accumulator B is enabled for accumulation and the Accumulator B Output Register is disabled for loading. When ACCB is LOW, no accumulation is performed and the Accumulator B Output Regis- ter is enabled for loading. ACCB is latched on the rising edge of CLK. SHENA — Filter A Shift Enable In Dual Filter Mode, SHENA enables or disables the loading of data into the Input (DIN11-0) and Filter A I/D Registers. When SHENA is LOW, data is latched into the Input/Cascade Registers and shifted through the I/D Registers on the rising edge of CLK. When SHENA is HIGH, data can not be loaded into the Input/Cascade Registers or shifted through the I/D Registers and their contents will not be changed. In Single Filter Mode, SHENA also enables or disables the loading of data into the Reverse Cascade Input (RIN11- 0 ), Cascade Output (COUT11-0), Reverse Cascade Output (ROUT11-0) and Filter B I/D Registers. It is important to note that in Single Filter Mode, both SHENA and SHENB should be connected together. Both must be active to enable data loading in Single Filter Mode. SHENA is latched on the rising edge of CLK. SHENB — Filter B Shift Enable In Dual Filter Mode, SHENB enables or disables the loading of data into the Reverse Cascade Input (RIN11-0), Cascade Output (COUT11-0), Reverse Cascade Output (ROUT3-0) and Filter B I/D Registers. When SHENB is LOW, data is latched into the Cascade Regis- ters and shifted through the I/D |
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Mô tả tương tự - LF3320QC15 |
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