công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
ADV7392 bảng dữ liệu(PDF) 10 Page - Analog Devices |
|
ADV7392 bảng dữ liệu(HTML) 10 Page - Analog Devices |
10 / 108 page ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet DIGITAL TIMING SPECIFICATIONS—1.8 V VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 1.89 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 10. Parameter Conditions1 Min Typ Max Unit VIDEO DATA AND VIDEO CONTROL PORT2, 3 Data Input Setup Time, t114 SD 1.4 ns ED/HD-SDR 1.9 ns ED/HD-DDR 1.9 ns ED (at 54 MHz) 1.6 ns Data Input Hold Time, t124 SD 1.4 ns ED/HD-SDR 1.5 ns ED/HD-DDR 1.5 ns ED (at 54 MHz) 1.3 ns Control Input Setup Time, t114 SD 1.4 ns ED/HD-SDR or ED/HD-DDR 1.2 ns ED (at 54 MHz) 1.0 ns Control Input Hold Time, t124 SD 1.4 ns ED/HD-SDR or ED/HD-DDR 1.0 ns ED (at 54 MHz) 1.0 ns Control Output Access Time, t134 SD 13 ns ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) 12 ns Control Output Hold Time, t144 SD 4.0 ns ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) 5.0 ns PIPELINE DELAY5 SD1 CVBS/Y-C Outputs (2×) SD oversampling disabled 68 Clock cycles CVBS/Y-C Outputs (8×) SD oversampling enabled 79 Clock cycles CVBS/Y-C Outputs (16×) SD oversampling enabled 67 Clock cycles Component Outputs (2×) SD oversampling disabled 78 Clock cycles Component Outputs (8×) SD oversampling enabled 69 Clock cycles Component Outputs (16×) SD oversampling enabled 84 Clock cycles ED1 Component Outputs (1×) ED oversampling disabled 41 Clock cycles Component Outputs (4×) ED oversampling enabled 49 Clock cycles Component Outputs (8×) ED oversampling enabled 46 Clock cycles HD1 Component Outputs (1×) HD oversampling disabled 40 Clock cycles Component Outputs (2×) HD oversampling enabled 42 Clock cycles Component Outputs (4×) HD oversampling enabled 44 Clock cycles RESET CONTROL RESET Low Time 100 ns 1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate. 2 Video data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391. 3 Video control: HSYNC and VSYNC. 4 Guaranteed by characterization. 5 Guaranteed by design. Rev. H | Page 10 of 108 |
Số phần tương tự - ADV7392_15 |
|
Mô tả tương tự - ADV7392_15 |
|
|
Link URL |
Chính sách bảo mật |
ALLDATASHEET.VN |
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |