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ADMC326 bảng dữ liệu(PDF) 9 Page - Analog Devices |
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ADMC326 bảng dữ liệu(HTML) 9 Page - Analog Devices |
9 / 32 page ADMC326 –9– REV. C • SPORT1 receive and transmit sections can generate unique interrupts on completing a data word transfer. • SPORT1 can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. An interrupt is generated after a data buffer transfer. • SPORT1 can be configured to have two external interrupts (IRQ0 and IRQ1), and the Flag In and Flag Out signals. The internally generated serial clock may still be used in this configuration. • SPORT1 has two data receive pins (DR1A and DR1B), which are internally multiplexed onto the one DR1 port of the SPORT1. The particular data receive pin selected is deter- mined by a bit in the MODECTRL register. PIN FUNCTION DESCRIPTION The ADMC326 is available in a 28-lead SOIC package and a 28-lead PDIP package. Table I describes the pins. Table I. Pin List Group # of Input/ Name Pins Output Function RESET 1 I Processor Reset Input SPORT1 1 6 I/O Serial Port 1 Pins (TFS1, RFS1, DT1, DR1A, DR1B, SCLK1) CLKOUT 1 1 O Processor Clock Output CLKIN, XTAL 2 I, O External Clock or Quartz Crystal Connection Point PIO0–PIO8 1 9 I/O Digital I/O Port Pins AUX0–AUX1 1 2 O Auxiliary PWM Outputs AH–CL 6 O PWM Outputs PWMTRIP 1 I PWM Trip Signal V1, V2, V3 3 I Analog Inputs VAUX0–VAUX2 3 I Auxiliary Analog Input ICONST 1 O ADC Constant Current Source VDD 1 Power Supply GND 1 Ground NOTE 1Multiplexed pins, selectable individually through the PIOSELECT and PIODATA1 registers. INTERRUPT OVERVIEW The ADMC326 can respond to 16 different interrupt sources with minimal overhead, five of which are internal DSP core interrupts and 11 are from the motor control peripherals. The five DSP core interrupts are SPORT1 receive (or IRQ0) and trans- mit (or IRQ1), the internal timer, and two software interrupts. The motor control peripheral interrupts are the nine program- mable I/Os and two from the PWM (PWMSYNC pulse and PWMTRIP). All motor control interrupts are multiplexed into the DSP core through the peripheral IRQ2 interrupt. The interrupts are internally prioritized and individually maskable. A detailed description of the entire interrupt system of the ADMC326 is presented later, following a more detailed description of each peripheral block. Memory Map The ADMC326 has two distinct memory types: program memory and data memory. In general, program memory contains user code and coefficients, while the data memory is used to store variables and data during program execution. Both program memory RAM and ROM are provided on the ADMC326. Pro- gram memory RAM is arranged as one contiguous 512 × 24-bit block, starting at address 0x0000. Program memory ROM is a 4K × 24-bit block located at address 0x0800. Data memory is arranged as a 512 × 16-bit block starting at address 0x3800. The motor control peripherals are memory mapped into a region of the data memory space starting at 0x2000. The complete program and data memory maps are given in Tables II and III, respectively. Table II. Program Memory Map Memory Address Range Type Function 0x0000–0x002F RAM Interrupt Vector Table 0x0030–0x01FF RAM User Program Memory 0x0200–0x07FF Reserved 0x0800–0x17FF ROM User Program Memory 0x1800–0x3FFF Reserved Table III. Data Memory Map Memory Address Range Type Function 0x0000–0x1FFF Reserved 0x2000–0x20FF Memory Mapped Registers 0x2100–0x37FF Reserved 0x3800–0x39FF RAM User Data Memory 0x3A00–0x3BFF RAM Reserved 0x3C00–0x3FFF Memory Mapped Registers SYSTEM INTERFACE Figure 4 shows a basic system configuration for the ADMC326 with an external crystal. ADMC326 XTAL CLKIN 10MHz CLKOUT RESET 33pF 33pF Figure 4. Basic System Configuration Clock Signals The ADMC326 can be clocked either by a crystal or a TTL- compatible clock signal. For normal operation, the CLKIN input cannot be halted, changed during operation, or operated below the specified minimum frequency. If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected to the CLKIN pin of the ADMC326. In this mode, with an external clock signal, the XTAL pin must be left unconnected. The ADMC326 uses an input clock with a frequency equal to half the instruction rate; a 10 MHz input clock yields a 50 ns processor cycle (which is equivalent to 20 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction rate, which is indicated by the CLKOUT signal when enabled. Because the ADMC326 includes an on-chip oscillator feedback circuit, an external crystal may be used instead of a clock source, as |
Số phần tương tự - ADMC326_15 |
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Mô tả tương tự - ADMC326_15 |
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