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ADM9690 bảng dữ liệu(PDF) 5 Page - Analog Devices |
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ADM9690 bảng dữ liệu(HTML) 5 Page - Analog Devices |
5 / 6 page ADM9690 –5– REV. A POWER SUPPLY AND WATCHDOG MONITORING CIRCUIT The ADM9690 contains a power supply voltage monitoring comparator and a watchdog timer monitor. Either VMON drop- ping outside tolerance or the watchdog timer timing out results in a reset sequence as discussed below. Two reset outputs are provided. RESET(1) and RESET(2). POWER FAIL/POWER-ON RESET When VMON falls below the reset threshold (4.4 V) both RESET outputs are forced low immediately. On power-up, RESET(1) will remain low for 50 milliseconds after VMON rises above the reset threshold. This provides a power-on reset for the microprocessor. RESET(2) remains active low for an additional 10 ms. RESET(1) is intended to WATCHDOG TRANSITION DETECTOR VCC VMON OSC SEL1 OSC SEL2 RESET(2) TIMER RESET(1) TIMER 4.31V ADM9690 RESET(1) RESET(2) WATCHDOG INPUT (WDI) GND WATCHDOG TIMEBASE Figure 6. Functional Block Diagram provide a power-on reset signal for the µP while RESET(2) is used to hold additional circuitry in a reset state until the µP has regained control following a power-up. The guaranteed minimum and maximum thresholds for the ADM9690 are 4.3 V and 4.5 V. Watchdog Timer RESET The watchdog timer circuit monitors the activity of the micro- processor in order to check that it is not stalled in an infinite loop. An output line on the processor may be used to toggle the Watchdog Input (WDI) line. If this line is not toggled within the selected timeout period, both RESET outputs are taken active (low). RESET(1) remains low for 50 ms and RESET(2) re- mains low for an additional 10 ms . Each transition (either positive-going or negative-going) of WDI after RESET(1) has gone inactive restarts the watchdog timer. The actual watchdog timeout period is adjustable using SEL1 and SEL2. Four timeout periods are selectable. Please refer to Table I. The watchdog timer is restarted at the end of RESET(1) (RESET(1) going high), whether the reset was caused by lack of activity on WDI or by VMON falling below the reset threshold. Table I. Watchdog Timeout SEL2 SEL1 Period tWD (ms) 0 0 0.75 0 1 1.5 1 0 12.5 11 25 VMON t 2 t 1 RESET(1) RESET(2) Figure 7. Power-On RESET Timing WDI t 2 t 1 RESET(1) RESET(2) t WD Figure 8. Watchdog RESET Timing |
Số phần tương tự - ADM9690_15 |
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Mô tả tương tự - ADM9690_15 |
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