Data Sheet

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

Rev. D | Page 7 of 16

RESET

TOP VIEW

(Not to Scale)

1

2

3

4

5

8

7

6

MR

PFO

NC

GND

PFI

NC = NO CONNECT

RESET

ADM708R/

ADM708S/

ADM708T

Figure 5. ADM708R/ADM708S/ADM708T

Table 4. Pin Function Descriptions ADM708R/ADM708S/ADM708T

Pin No.

Mnemonic

Description

1

MR

Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven from TTL, CMOS

logic, or from a manual reset switch because it is internally debounced. An internal 70 μA pull-up current holds

the input high when floating.

2

Power Supply Input.

3

GND

Ground. Ground reference for all signals (0 V).

4

PFI

Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less than 1.25 V, PFO

5

PFO

Power-Fail Output. PFO is the output from the power-fail comparator. It goes low when PFI is less than 1.25 V.

6

NC

No Connect.

7

RESET

timeout does not trigger RESET unless WDO is connected to MR.

8

RESET

Logic Output. RESET is an active high output suitable for systems that use active high reset logic. It is the

inverse of RESET.