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ADD8502 bảng dữ liệu(PDF) 2 Page - Analog Devices |
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ADD8502 bảng dữ liệu(HTML) 2 Page - Analog Devices |
2 / 16 page REV. 0 –2– ADD8502–SPECIFICATIONS RL 100 CL 16nF VCOM Figure 1. Slew Rate Diagram (@ VDD = 5.0 V, 40 C ≤ T A ≤ 85 C, unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Unit SYSTEM ACCURACY VOUT Error 320 mV Swing Error 1 (VPn – VNn) – (VPi – VNi)1 17 mV Mean Error 2 (VPn+ VNn)/2 – (VPi + VNi)/2) 3 21 mV Mean Error between Adjacent Channels 3 321 mV Mean Error between V0 and V4 4 325 mV DAC ACCURACY Resolution 10 Bits Differential Nonlinearity DNL ±0.25 LSB Integral Nonlinearity 5 INL ±0.5 LSB Offset Error ±0.4 % of FSR Gain Error ±0.15 % of FSR OUTPUT CHARACTERISTICS Output Current IOUT (VDD – 1 V) 25 mA Short Circuit Current ISC Short to Ground 60 mA Output Leakage Current in High-Z Mode ILEAKAGE High-Z Mode 0.01 1.0 µA Slew Rate SR RL = 100 k Ω 1.25 V/ µs Settling Time to 1% tS V0 to V4 Step Size 8 12 µs Slew Rate 5 SR LD =100 Ω Series 16 nF 0.7 V/ µs Settling Time to 1%5 tS V0 to V4 Step Size 8 12 µs Phase Margin φo67 Degrees VCOM SWITCHES ACTIVE IMPEDANCE COM to VDD Z See Table IV 25 50 Ω COM to GND Z 25 50 Ω COM to COM_M Z I = 20 mA 25 50 Ω COM to V4 Z 25 50 Ω MASK PROGRAMMABLE RESISTOR CHAIN Resistor Matching RMATCH Any Two Segments between 1 % 512 Resistor String POWER SUPPLY Supply Voltage VDD 4.5 5 5.5 V Supply Current ISY VDD = 5 V; No Load 190 270 400 µA Shutdown Supply Current ISY-GLB Full Shutdown Mode 0.2 1 µA Sleep Supply Current ISY-GS1-3 Mid 3 Buffers Shutdown 140 175 210 µA Shutdown Recovery Time Global PD to 1% 23 30 µs Sleep Recovery Time V1–V3 Off to 1% 10 15 µs LOGIC SUPPLY Logic Input Voltage Level VL 2.3 3.3 5.5 V Logic Input Current IVL 0.01 1 µA DIGITAL I/O Digital Input High Voltage VIH VL 0.7 V Digital Input Low Voltage VIL VL 0.3 V Digital Input Current IIN GND ≤ V IN ≤ 5.5 V ±1 µA Digital Input Capacitance CIN 10 pF NOTES 1Swing error is a comparison of measured V OUT step versus theoretical VOUT step. Theoretical values can be found on the Mask Tap Point Option sheet. 2Mean error is measured V OUT mean versus theoretical VOUT mean (see Figure 3). 3Mean errors between two adjacent channels versus theoretical (see Figure 3). 4Mean errors between V0 and V4 versus theoretical (see Figure 3). 5Slew rate and settling time are measured between the output resistor and the capacitor (see Figure 1) . Specifications subject to change without notice. |
Số phần tương tự - ADD8502_15 |
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Mô tả tương tự - ADD8502_15 |
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