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ADC912A bảng dữ liệu(PDF) 1 Page - Analog Devices |
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ADC912A bảng dữ liệu(HTML) 1 Page - Analog Devices |
1 / 16 page REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADC912A One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 CMOS Microprocessor-Compatible 12-Bit A/D Converter FUNCTIONAL BLOCK DIAGRAM THREE-STATE OUTPUT DRIVERS THREE-STATE OUTPUT DRIVERS CLOCK OSCILLATOR CONTROL LOGIC MULTIPLEXER 12-BIT LATCH 12-BIT DAC SUCCESSIVE APPROXIMATION REGISTER ADC912A AGND VREFIN AIN VDD VSS CLK OUT CLK IN HBEN CS RD BUSY D11 D7 D8 D4 DGND D3/11 D0/8 5k 48 8 ANALOG INPUT 100 90 10 0% TRANSITION NOISE Figure 2. Transition Noise Cross Plot FEATURES Low Cost Low Transition Noise between Code 12-Bit Accurate 1/2 LSB Nonlinearity Error over Temperature No Missing Codes at All Temperatures 10 s Conversion Time Internal or External Clock 8- or 16-Bit Data Bus Compatible Improved ESD Resistant Design Latchup Resistant Epi-CMOS Processing Low 95 mW Power Consumption Space-Saving 24-Lead 0.3" DIP, or 24-Lead SOIC APPLICATIONS Data Acquisition Systems DSP System Front End Process Control Systems Portable Instrumentation GENERAL DESCRIPTION The ADC912A is a monolithic 12-bit accurate CMOS A/D converter. It contains a complete successive-approximation A/D converter built with a high-accuracy D/A converter, a precision bipolar transistor high-speed comparator, and successive- approximation logic including three-state bus interface for logic compatibility. The accuracy of the ADC912A results from the addition of precision bipolar transistors to Analog Devices’ advanced-oxide isolated silicon-gate CMOS process. Particular attention was paid to the reduction of transition noise between adjacent codes achieving a 1/6 LSB uncertainty. The low noise design produces the same digital output for dc analog inputs not located at a transition voltage, see Figures 1 and 2. NPN digital output transistors provide excellent bus interface timing, 125 ns access and bus disconnect time which results in faster data transfer without the need for wait states. An external 1.25 MHz clock provides a 10 µs conversion time. In stand-alone applications an internal clock can be used with external crystal. An external negative five-volt reference sets the 0 V to 10 V input range. Plus 5 V and minus 12 V power supplies result in 95 mW of total power consumption. 256 0 64 128 192 2045 2049 2048 2047 2046 256 SUCCESSIVE CONVERSIONS WITH AIN = 4.99756V OUTPUT CODE – Decimal Figure 1. Code Repetition |
Số phần tương tự - ADC912A_15 |
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Mô tả tương tự - ADC912A_15 |
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