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AD14060L bảng dữ liệu(PDF) 8 Page - Analog Devices

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AD14060/AD14060L
Rev. B | Page 8 of 48
MEMORY READ—BUS MASTER
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the AD14060/AD14060L is the bus master accessing external memory space.
These switching characteristics also apply for bus master synchronous read/write timing (see the Synchronous Read/Write—Bus Master
section). If these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa).
Table 8. Specifications
5 V
3.3 V
Parameter
Min
Max
Min
Max
Unit
Timing Requirements:
tDAD
Address, Delay to Data Valid1, 2
17.5 + DT + W
17.5 + DT + W
ns
tDRLD
RD Low to Data Valid1
11.5 + 5 DT/8 + W
11.5 + 5 DT/8 + W
ns
tHDA
Data Hold from Address3
1
1
ns
tHDRH
Data Hold from RD High3
2.5
2.5
ns
tDAAK
ACK Delay from Address2, 4
13.5 + 7 DT/8 + W
13.5 + 7 DT/8 + W
ns
tDSAK
ACK Delay from RD Low4
7.5 + DT/2 + W
7.5 + DT/2 + W
ns
Switching Characteristics:
tDRHA
Address Hold after RD High
−0.5 + H
−0.5 + H
ns
tDARL
Address to RD Low2
1.5 + 3 DT/8
1.5 + 3 DT/8
ns
tRW
RD Pulse Width
12.5 + 5 DT/8 + W
12.5 + 5 DT/8 + W
ns
tRWR
RD High to WR, RD, DMAGx Low
8 + 3 DT/8 + HI
8 + 3 DT/8 + HI
ns
tSADADC
Address Setup before ADRCLK High2
−0.5 + DT/4
−0.5 + DT/4
ns
W = number of wait states specified in WAIT register × tCK.
HI = tCK, if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise, HI = 0.
H = tCK, if an address hold cycle occurs as specified in WAIT register; otherwise, H = 0.
1 Data delay/setup: User must meet tDAD, tDRLD, or synchronous specification, tSSDATI.
2 For MSx, SW, BMS, the falling edge is referenced.
3 Data hold: User must meet tHDA, tHDRH, or synchronous specification, tHDATI. See the
section for the calculation of hold times given
capacitive and dc loads.
System Hold Time Calculation Example
4 ACK delay/setup: User must meet tDSAK, tDAAK, or synchronous specification, tSACKC.
ADDRESS
MSx, SW
BMS
WR, DMAG
ACK
DATA
ADRCLK
(OUT)
tDRHA
tDARL
tDRLD
tHDRH
tDSAK
tRWR
tDAAK
tDAD
tHDA
tSADADC
tRW
RD
Figure 7. Memory Read—Bus Master


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