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AD9984A bảng dữ liệu(PDF) 10 Page - Analog Devices |
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AD9984A bảng dữ liệu(HTML) 10 Page - Analog Devices |
10 / 44 page AD9984A Rev. 0 | Page 10 of 44 Mnemonic Function Description FILT External Filter Connection For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 8 to this pin. For optimal performance, minimize noise and parasitics on this node. For more information, see the PCB Layout Recommendations section. HSOUT Horizontal Sync Output This pin is a reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be programmed via serial bus registers. By maintaining alignment with DATACK and the main data outputs (RED[9:0], GREEN[9:0], BLUE[9:0]), data timing with respect to Hsync can always be determined. VSOUT/A0 Vertical Sync Output (VSOUT) This pin has dual functionality. VSOUT can either be a separated Vsync from a composite signal or a direct pass through of the Vsync signal. The polarity of this output can be controlled via a serial bus bit. The placement and duration in all modes can be set by the graphics transmitter or the duration can be set by Register 0x14, Bit 1 and Register 0x15, Bits[7:0]. This VSOUT function does not affect the A0 function. Serial Port Address Input 0 (A0) A0 selects the LSB of the serial port device address, allowing two parts from Analog Devices, Inc., to be on the same serial bus. A high impedance (10 kΩ), external pull-up resistor enables this pin to be read at power-up as 1. This A0 function does not interfere with the VSOUT function. For more details on A0, see the description in the 2-Wire Serial Control Port section. SOGOUT Sync-On-Green Slicer Output This pin outputs one of four possible signals (controlled by Register 0x1D, Bits[1:0]): raw SOGINx, raw HSYNCx, regenerated Hsync from the filter, or the filtered Hsync. See Figure 9 to view how this pin is connected. Other than slicing off SOG, the output from this pin receives no additional processing on the AD9984A. Vsync separation is performed via the sync separator. O/E FIELD Odd/Even Field Bit for Interlaced Video This output identifies whether the current field (in an interlaced signal) is odd or even. SDA Serial Port Data I/O Data I/O for the I2C® serial port. SCL Serial Port Data Clock Clock for the I2C serial port. RED[9:0] Data Output, Red Channel GREEN[9:0] Data Output, Green Channel BLUE[9:0] Data Output, Blue Channel The main data outputs. Bit 9 is the MSB. The delay from pixel sampling time to output is fixed. When the sampling time is changed by adjusting the phase register, the output timing is shifted as well. The DATACK and HSOUT outputs are also moved to maintain the timing relationship among the signals. DATACK Data Clock Output This is the main clock output signal used to strobe the output data and HSOUT into external logic. Four possible output clocks can be selected with Register 0x20, Bits[7:6]. Three of these are related to the pixel clock (pixel clock, 90° phase-shifted pixel clock, and 2× frequency pixel clock). They are produced by the internal PLL clock generator or by EXTCK, and are synchronous with the pixel sampling clock. The fourth option for the data clock output is an internally generated 0.5× pixel clock. The sampling time of the internal pixel clock can be changed by adjusting the phase register (Register 0x04). When this is changed, the pixel-related DATACK timing is also shifted. The data (RED[9:0], GREEN[9:0], BLUE[9:0]), DATACK, and HSOUT outputs are moved to maintain the timing relationship among the signals. VD (1.8 V) Main Power Supply These pins supply power to the main elements of the circuit. They should be as quiet and as filtered as possible. VDD (1.8 V to 3.3 V) Digital Output Power Supply A large number of output pins (up to 35) switching at high speed (up to 170 MHz) generates large amounts of power supply transients (noise). These supply pins are identified separately from the VD pins. As a result, special care must be taken to minimize output noise transferred into the sensitive analog circuitry. If the AD9984A is interfacing with lower voltage logic, VDD can be connected to a lower supply voltage (as low as 1.8 V) for compatibility. PVD (1.8 V) Clock Generator Power Supply The most sensitive portion of the AD9984A is the clock generation circuitry. These pins provide power to the clock PLL and help the user design for optimal performance. The designer should provide quiet, noise-free power to these pins. DAVDD (1.8 V) Digital Input Power Supply This supplies power to the digital logic. It is recommended to connect this pin to the VD supply. GND Ground The ground return for all on-chip circuitry. It is recommended that the AD9984A be assembled on a single solid ground plane with careful attention to ground current paths. |
Số phần tương tự - AD9984A_15 |
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Mô tả tương tự - AD9984A_15 |
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