công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

AD9887 bảng dữ liệu(PDF) 11 Page - Analog Devices

tên linh kiện AD9887
Giải thích chi tiết về linh kiện  Dual Interface for Flat Panel Displays
Download  40 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  AD [Analog Devices]
Trang chủ  http://www.analog.com
Logo AD - Analog Devices

AD9887 bảng dữ liệu(HTML) 11 Page - Analog Devices

Back Button AD9887_15 Datasheet HTML 7Page - Analog Devices AD9887_15 Datasheet HTML 8Page - Analog Devices AD9887_15 Datasheet HTML 9Page - Analog Devices AD9887_15 Datasheet HTML 10Page - Analog Devices AD9887_15 Datasheet HTML 11Page - Analog Devices AD9887_15 Datasheet HTML 12Page - Analog Devices AD9887_15 Datasheet HTML 13Page - Analog Devices AD9887_15 Datasheet HTML 14Page - Analog Devices AD9887_15 Datasheet HTML 15Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 40 page
background image
REV. 0
AD9887
–11–
Either or both signals may be used, depend-
ing on the timing mode and interface design
employed.
HSOUT
Horizontal Sync Output
A reconstructed and phase-aligned version of
the Hsync input. Both the polarity and dura-
tion of this output can be programmed via
serial bus registers.
By maintaining alignment with DATACK,
DATACK, and Data, data timing with
respect to horizontal sync can always be
determined.
SOGOUT
Sync-On-Green Slicer Output
This pin can be programmed to output
either the output from the Sync-On-Green
slicer comparator or an unprocessed but
delayed version of the HSYNC input. See
the Sync Block Diagram to view how this
pin is connected.
(Note: The output from this pin is the sliced
SOG, without additional processing from the
AD9887.)
Analog Interface
REFOUT
Internal Reference Output
Output from the internal 1.25 V bandgap refer-
ence. This output is intended to drive relatively
light loads. It can drive the AD9887 Reference
Input directly, but should be externally buff-
ered if it is used to drive other loads as well.
The absolute accuracy of this output is
±4%,
and the temperature coefficient is
±50 ppm,
which is adequate for most AD9887 appli-
cations. If higher accuracy is required, an
external reference may be employed instead.
If an external reference is used, connect this
pin to ground through a 0.1
µF capacitor.
REFIN
Reference Input
The reference input accepts the master refer-
ence voltage for all AD9887 internal circuitry
(1.25 V
±10%). It may be driven directly by
the REFOUT pin. Its high impedance pre-
sents a very light load to the reference source.
This pin should always be bypassed to Ground
with a 0.1
µF capacitor.
FILT
External Filter Connection
For proper operation, the pixel clock genera-
tor PLL requires an external filter. Connect
the filter shown Figure 7 to this pin. For
optimal performance, minimize noise and
parasitics on this node.
Power Supply
VD
Main Power Supply
These pins supply power to the main elements
of the circuit. It should be filtered to be as
quiet as possible.
VDD
Digital Output Power Supply
These supply pins are identified separately
from the VD pins so special care can be taken
to minimize output noise transferred into the
sensitive analog circuitry.
If the AD9887 is interfacing with lower-
voltage logic, VDD may be connected to a
lower supply voltage (as low as 2.2 V) for
compatibility.
PVD
Clock Generator Power Supply
The most sensitive portion of the AD9887 is
the clock generation circuitry. These pins
provide power to the clock PLL and help the
user design for optimal performance. The
designer should provide noise-free power to
these pins.
GND
Ground
The ground return for all circuitry on chip.
It is recommended that the application circuit
board have a single, solid ground plane.
THEORY OF OPERATION (INTERFACE DETECTION)
Active Interface Detection and Selection
The AD9887 includes circuitry to detect whether or not an
interface is active.
For detecting the analog interface, the circuitry monitors the
presence of HSYNC, VSYNC, and Sync-on-Green. The result of
the detection circuitry can be read from the 2-wire serial inter-
face bus at address 11H Bits 7, 6, and 5 respectively. If one of
these sync signals disappears, the maximum time it takes for the
circuitry to detect it is 100 ms.
There are two stages for detecting the digital interface. The first
stage searches for the presence of the digital interface clock.
The circuitry for detecting the digital interface clock is active
even when the digital interface is powered down. The result of
this detection stage can be read from the 2-wire serial interface
bus at address 11H Bit 4. If the clock disappears, the maximum
time it takes for the circuitry to detect it is 100 ms. The second
stage attempts to detect DE on the digital interface. Detection is
accomplished when 32 DEs have been counted. DE can only be
detected when the digital interface is powered up, so it is not
always active. The DE detection circuitry is one of the logic
inputs used to set the SyncDT output pin (Pin 136). The logic
for the SyncDT pin is [DE detect] OR [HSYNC detect].
There is an override for the automatic interface selection. It is
the AIO bit (Active Interface Override). When the AIO bit is set
to Logic 0, the automatic circuitry will be used. When the AIO
bit is set to Logic 1, the AIS bit will be used to determine the
active interface rather than the automatic circuitry.


Số phần tương tự - AD9887_15

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
logo
Analog Devices
AD9887/PCB AD-AD9887/PCB Datasheet
321Kb / 40P
   Dual Interface for Flat Panel Displays
REV. 0
AD9887A AD-AD9887A Datasheet
384Kb / 44P
   Dual Interface for Flat Panel Displays
REV. 0
AD9887A AD-AD9887A Datasheet
918Kb / 52P
   Dual Interface for Flat Panel Display
REV. B
AD9887AKS-100 AD-AD9887AKS-100 Datasheet
384Kb / 44P
   Dual Interface for Flat Panel Displays
REV. 0
AD9887AKS-100 AD-AD9887AKS-100 Datasheet
918Kb / 52P
   Dual Interface for Flat Panel Display
REV. B
More results

Mô tả tương tự - AD9887_15

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
logo
Analog Devices
AD9887 AD-AD9887 Datasheet
321Kb / 40P
   Dual Interface for Flat Panel Displays
REV. 0
AD9882 AD-AD9882 Datasheet
370Kb / 36P
   Dual Interface for Flat Panel Displays
REV. A
AD9882A AD-AD9882A_15 Datasheet
985Kb / 40P
   Dual Interface for Flat Panel Displays
REV. 0
AD9882A AD-AD9882A Datasheet
984Kb / 40P
   Dual Interface for Flat Panel Displays
REV. 0
AD9882 AD-AD9882_15 Datasheet
376Kb / 36P
   Dual Interface for Flat Panel Displays
REV. A
AD9887A AD-AD9887A Datasheet
384Kb / 44P
   Dual Interface for Flat Panel Displays
REV. 0
AD9886 AD-AD9886 Datasheet
248Kb / 32P
   Analog Interface for Flat Panel Displays
REV. 0
AD9886 AD-AD9886_15 Datasheet
248Kb / 32P
   Analog Interface for Flat Panel Displays
REV. 0
AD9883 AD-AD9883 Datasheet
177Kb / 24P
   110 MSPS Analog Interface for Flat Panel Displays
REV. 0
AD9887A AD-AD9887A_15 Datasheet
918Kb / 52P
   Dual Interface for Flat Panel Display
REV. B
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40


bảng dữ liệu tải về

Go To PDF Page


Link URL




Chính sách bảo mật
ALLDATASHEET.VN
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com