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AD9882 bảng dữ liệu(PDF) 5 Page - Analog Devices |
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AD9882 bảng dữ liệu(HTML) 5 Page - Analog Devices |
5 / 36 page REV. A AD9882 –5– Test AD9882KST Parameter Conditions Temp Level Min Typ Max Unit AC SPECIFICATIONS Intra-Pair (+ to –) Differential Input Skew (TDPS) Full IV 360 ps Channel-to-Channel Differential Full IV 1 Clock Input Skew (TCCS) Period Low-to-High Transition Time for Data (DLHT)Output Drive = High, CL = 10 pF Full IV 2.2 ns Output Drive = Med, CL = 7 pF Full IV 2.5 ns Output Drive = Low, CL = 5 pF Full IV 3.2 ns Low-to-High Transition Time for DATACK (DLHT)Output Drive = High, CL = 10 pF Full IV 1.0 ns Output Drive = Med, CL = 7 pF Full IV 1.6 ns Output Drive = Low, CL = 5 pF Full IV 2.1 ns High-to-Low Transition Time for Data (DHLT)Output Drive = High, CL = 10 pF Full IV 2.2 ns Output Drive = Med, CL = 7 pF Full IV 1.9 ns Output Drive = Low, CL = 5 pF Full IV 1.7 ns High-to-Low Transition Time for DATACK (DHLT)Output Drive = High, CL = 10 pF Full IV 1.0 ns Output Drive = Med, CL = 7 pF Full IV 1.0 ns Output Drive = Low, CL = 5 pF Full IV 1.4 ns Data-to-Clock Skew 4 Full IV –0.5 +2.0 ns Duty Cycle, DATACK 4 Full IV 40 46 50 % DATACK Frequency (FCIP) Full VI 25 112 MHz NOTES 1The typical pattern contains a grayscale area, Output Drive = High. 2DATACK Load = 10 pF, Data Load = 10 pF. 3The worst-case pattern contains a black and white checkerboard pattern, Output Drive = High. 4DRIVE STRENGTH = 11 Specifications subject to change without notice. |
Số phần tương tự - AD9882_15 |
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Mô tả tương tự - AD9882_15 |
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