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CD4093BMS bảng dữ liệu(PDF) 1 Page - Intersil Corporation |
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CD4093BMS bảng dữ liệu(HTML) 1 Page - Intersil Corporation |
1 / 9 page 7-1074 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 Pinout CD4093BMSMS TOP VIEW Functional Diagram A B J = A · B K = C · D C D VSS VDD H G M = G · H L = E · F F E 1 2 3 4 5 6 7 14 13 12 11 10 9 8 A B J K C D VSS VDD H G M L F E 1 2 3 4 5 6 7 14 13 12 11 10 9 8 J = A · B L = E · F M = G · H K = C · D Features • High Voltage Types (20V Rating) • Schmitt Trigger Action on Each Input With No External Components • Hysteresis Voltage Typically 0.9V at VDD = 5V and 2.3V at VDD = 10V • Noise Immunity Greater than 50% • No Limit on Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1 µA at 18V Over Full Pack- age Temperature Range, 100nA at 18V and +25oC • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications • Wave and Pulse Shapers • High Noise Environment Systems • Monostable Multivibrators • Astable Multivibrators • NAND Logic Description CD4093BMS consists of four Schmitt trigger circuits. Each circuit functions as a two input NAND gate with Schmitt trig- ger action on both inputs. The gate switches at different points for positive and negative going signals. The difference between the positive voltage (VP) and the negative voltage (VN) is defined as hysteresis voltage (VH) (see Figure 1). The CD4093BMS is supplied in these 14 lead outline pack- ages: Braze Seal DIP H4H Frit Seal DIP H1B Ceramic Flatpack H3W File Number 3330 December 1992 CD4093BMS CMOS Quad 2-Input NAND Schmitt Triggers |
Số phần tương tự - CD4093BMS |
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Mô tả tương tự - CD4093BMS |
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