AD7840

REV. B

–8–

As in the parallel mode, the LDAC signal controls the loading

of data to the DAC latch. Normally, data is loaded to the DAC

latch on the falling edge of LDAC. However, if LDAC is held

low, then serial data is loaded to the DAC latch on the sixteenth

falling edge of SCLK. If LDAC goes low during the transfer of

serial data to the input latch, no DAC latch update takes place

on the falling edge of LDAC. If LDAC stays low until the serial

transfer is completed, then the update takes place on the six-

teenth falling edge of SCLK. If LDAC returns high before the

serial data transfer is completed, no DAC latch update takes

place. Figure 9 shows the simplified serial input control logic for

the AD7840.

Figure 9. AD7840 Simplified Serial Input Control Logic

AD7840 DYNAMIC SPECIFICATIONS

The AD7840 is specified and 100% tested for dynamic perfor-

mance specifications as well as traditional dc specifications such

as integral and differential nonlinearity. These ac specifications

are required for the signal processing applications such as

speech synthesis, servo control and high speed modems. These

applications require information on the DAC’s effect on the

spectral content of the signal it is creating. Hence, the param-

eters for which the AD7840 is specified include signal-to-noise

ratio, harmonic distortion and peak harmonics. These terms are

discussed in more detail in the following sections.

Signal-to-Noise Ratio (SNR)

SNR is the measured signal-to-noise ratio at the output of the

DAC. The signal is the rms magnitude of the fundamental.

Noise is the rms sum of all the nonfundamental signals up to

half the sampling frequency (fs/2) excluding dc. SNR is depen-

dent upon the number of quantization levels used in the digiti-

zation process; the more levels, the smaller the quantization

noise. The theoretical signal to noise ratio for a sine wave out-

put is given by

SNR = (6.02N + 1.76) dB

(1)

where N is the number of bits. Thus for an ideal 14-bit con-

verter, SNR = 86 dB.

Figure 10 shows a typical 2048 point Fast Fourier Transform

(FFT) plot of the AD7840KN with an output frequency of

1 kHz and an update rate of 100 kHz. The SNR obtained from

this graph is 81.8 dB. It should be noted that the harmonics are

taken into account when calculating the SNR.

Figure 10. AD7840 FFT Plot

Effective Number of Bits

The formula given in (1) relates the SNR to the number of bits.

Rewriting the formula, as in (2) it is possible to get a measure of

performance expressed in effective number of bits (N).

N

= SNR −1.76

6.02

(2)

The effective number of bits for a device can be calculated

directly from its measured SNR.

Harmonic Distortion

Harmonic distortion is the ratio of the rms sum of harmonics to

the fundamental. For the AD7840, total harmonic distortion

(THD) is defined as

THD

= 20 log

V

2

3

4

5

6

2

V

1

sixth harmonic. The THD is also derived from the 2048-point

FFT plot.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the DAC output

spectrum (up to fs/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification will be

determined by the largest harmonic in the spectrum, but for

parts where the harmonics are buried in the noise floor the peak

will be a noise peak.

Testing the AD7840

A simplified diagram of the method used to test the dynamic

performance specifications is outlined in Figure 11. Data is

loaded to the AD7840 under control of the microcontroller and

associated logic at a 100 kHz update rate. The output of the

AD7840 is applied to a ninth order, 50 kHz, low-pass filter. The

output of the filter is in turn applied to a 16-bit accurate digi-

tizer. This digitizes the signal and the microcontroller generates

an FFT plot from which the dynamic performance of the

AD7840 can be evaluated.