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CD4031BMS bảng dữ liệu(PDF) 1 Page - Intersil Corporation

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CD4031BMS bảng dữ liệu(HTML) 1 Page - Intersil Corporation

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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CD4031BMS
CMOS 64-Stage Static Shift Register
Description
The CD4031BMS is a static shift register that contains 64 D-
type, master-slave flip-flop stages and one stage which is a
D-type master flip-flop only (referred to as a 1/2 stage).
The logic level present at the DATA input is transferred into
the first stage and shifted one stage at each positive-going
clock transition. Maximum clock frequencies up to 12MHz
(typical) can be obtained. Because fully static operation is
allowed, information can be permanently stored with the
clock line in either the low or high state. The CD4031BMS
has a MODE CONTROL input that, when in the high state,
allows operation in the recirculating mode. The MODE CON-
TROL input can also be used to select between two sepa-
rate data sources. Register packages can be cascaded and
the clock lines driven directly for high-speed operation. Alter-
natively, a delayed clock output (CLD) is provided that
enables cascading register packages while allowing reduced
clock drive fan-out and transition-time requirements. A third
cascading option makes use of the Q’ output from the 1/2
stage, which is available on the next negative-going transi-
tion of the clock after the Q output occurs. This delayed out-
put, like the delayed clock CLD, is used with clocks having
slow rise and fall times.
The CD4031BMS is supplied in these 16 lead outline pack-
ages:
Braze Seal DIP
H4X
Frit Seal DIP
H1F
Ceramic Flatpack
H6W
Features
• High Voltage Type (20V Rating)
• Fully Static Operation: DC to 12MHz (typ.) at VDD -
VSS = 15V
• Standard TTL Drive Capability on Q Output
• Recirculation Capability
• Three Cascading Modes:
- Direct Clocking for High-Speed Operation
- Delayed Clocking for Reduced Clock Drive Require-
ments
- Additional 1/2 Stage for Slow Clocks
• 100% Tested For Quiescent Current at 20V
• Maximum Input Current of 1
µA at 18V Over Full
Package-Temperature Range;
- 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Serial Shift Registers
• Time Delay Circuits
December 1992
File Number
3306
Pinout
CD4031BMS
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
DATA IN 2
CLOCK INHIBIT
NC
NC
Q’
Q
VSS
Q
VDD
NC
NC
NC
NC
MODE CONTROL
CLD
DATA IN 1
RECIRCULATE
NC = NO CONNECTION
Functional Diagram
CONTROL
LOGIC
64
STAGES
CLOCK
LOGIC
1/2
STAGE
DATA 1
IN
MODE
CONT.
RECIRC
DATA 2
IN
CLOCK
IN
VDD = 16
VSS = 8
NC = 3, 4, 11, 12, 13, 14
DELAYED
CLOCK
OUT
DATA
OUT
6
DATA
OUT
7
Q’
5
15
10
1
2
9
CL
CL


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