CD4027BMS datasheet(4/8 Pages) INTERSIL

tên linh kiện	CD4027BMS

Giải thích chi tiết về linh kiện	CMOS Dual J-K Master-Slave Flip-Flop

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Speciﬁcations CD4027BMS

Output Current (Source)

IOH15

VDD =15V, VOUT = 13.5V

1, 2

+125oC

-

-2.4

mA

-55oC

-

-4.2

mA

Input Voltage Low

VIL

VDD = 10V, VOH > 9V, VOL < 1V

1, 2

+25oC, +125oC,

-55oC

-3

V

Input Voltage High

VIH

VDD = 10V, VOH > 9V, VOL < 1V

1, 2

+25oC, +125oC,

-55oC

7-

V

Propagation Delay

Clock To Q, Q

TPHL1

TPLH1

VDD = 10V

1, 2, 3

+25oC

-

130

ns

VDD = 15V

1, 2, 3

+25oC

-

90

ns

Propagation Delay

Set To Q, Reset To Q

TPLH2

VDD = 10V

1, 2, 3

+25oC

-

130

ns

VDD = 15V

1, 2, 3

+25oC

-

90

ns

Propagation Delay

Set To Q, Reset To Q

TPHL3

VDD = 10V

1, 2, 3

+25oC

-

170

ns

VDD = 15V

1, 2, 3

+25oC

-

120

ns

Transition Time

TTHL

TTLH

VDD = 10V

1, 2, 3

+25oC

-

100

ns

VDD = 15V

1, 2, 3

+25oC

-

80

ns

Maximum Clock Input

Frequency Toggle Mode

Input TR, TF = 5ns

FCL

VDD = 10V

1, 2, 3

+25oC

8

-

MHz

VDD = 15V

1, 2, 3

+25oC

12

-

MHz

Minimum Data Setup

Time

TS

VDD = 5V

1, 2, 3

+25oC

-

200

ns

VDD = 10V

1, 2, 3

+25oC

-

75

ns

VDD = 15V

1, 2, 3

+25oC

-

50

ns

Minimum Set or Reset

Pulse Width

TW

VDD = 5V

1, 2, 3

+25oC

-

180

ns

VDD = 10V

1, 2, 3

+25oC

-

80

ns

VDD = 15V

1, 2, 3

+25oC

-

50

ns

Minimum Clock Pulse

Width

TW

VDD = 5V

1, 2, 3

+25oC

-

140

ns

VDD = 10V

1, 2, 3

+25oC

-

60

ns

VDD = 15V

1, 2, 3

+25oC

-

40

ns

Clock Input Rise Or Fall

Time (Note 5)

TRCL

TFCL

VDD = 5V

1, 2, 3, 4

+25oC-

45

µs

VDD = 10V

1, 2, 3, 4

+25oC-

5

µs

VDD = 15V

1, 2, 3, 4

+25oC-

2

µs

Input Capacitance

CIN

1, 2

+25oC

-

7.5

pF

NOTES:

1. All voltages referenced to device GND.

2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized

on initial design release and upon design changes which would affect these characteristics.

3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

4. If more than one unit is cascaded in a parallel clocked operation, trCL should be made less than or equal to the sum of the fixed propa-

gation delay time at 15pF and the transition time of the output driving stage for the estimated capacitive load.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER

SYMBOL

CONDITIONS

NOTES

TEMPERATURE

LIMITS

UNITS

MIN

MAX

Supply Current

IDD

VDD = 20V, VIN = VDD or GND

1, 4

+25oC

-

7.5

µA

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

(Continued)

PARAMETER

SYMBOL

CONDITIONS

NOTES

TEMPERATURE

LIMITS

UNITS

MIN

MAX

Số phần tương tự - CD4027BMS

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
Renesas Technology Corp	CD4027BMS	337Kb / 8P	CMOS Dual J-KMaster-Slave Flip-Flop December 1992

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