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CD40182BMS bảng dữ liệu(PDF) 1 Page - Intersil Corporation |
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CD40182BMS bảng dữ liệu(HTML) 1 Page - Intersil Corporation |
1 / 9 page 7-1410 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CD40182BMS CMOS Look-Ahead Carry Generator Description The CD40182BMS is a high-speed look-ahead carry gener- ator capable of anticipating a carry across four binary adders or groups of adders. The CD40182BMS is cascadable to perform full look-ahead across n-bit adders. Carry, propa- gate-carry, and generate-carry functions are provided as enumerated in the terminal designation below. The CD40182BMS, when used in conjuction with the CD40181BMS arithmetic logic unit (ALU), provides full high- speed look-ahead carry capability for up to n-bit words. Each CD40182BMS generates the look-ahead (anticipated carry) across a group of four ALU’s. In addition, other CD40182BMS’s may be employed to anticipate the carry across sections of four look-ahead blocks up to n-bits. Carry inputs and outputs of the CD40181BMS are active-high logic, and carry-generate (G) and carry-propagate (P) out- puts are active-low. Therefore the inputs and outputs of the CD40182BMS are compatible. The CD40182BMS is supplied in these 16-lead outline packages: The CD40182BMS is similar to industry type MC14582. Braze Seal DIP H4V Frit Seal DIP H1E Ceramic Flatpack H6P Features • High Voltage Type (20V Rating) • Generates High-Speed Carry Across Four Adders or Adder Groups • High-Speed Operation - tPHL, tPLH =100 ns (typ) at VDD = 10V • Cascadable for Fast Carries Over N Bits • Designed for Use with CD40181BMS ALU • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Standardized Symmetrical Output Characteristics • Maximum Input Current of 1 µA at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications • High-Speed Parallel Arithmetric Units • Multi-Level Look-Ahead Carry Generation for Long Word Lengths December 1992 File Number 3362 Pinout CD40182BMS TOP VIEW 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 G1 P1 G0 P0 G3 P3 VSS P VDD G2 Cn Cn + x Cn + y G Cn + z P2 Functional Diagram G0 G1 G2 G3 Cn 3 1 14 5 13 P0 P1 P2 P3 4 2 15 6 G P 12 11 9 7 10 P G Cn + x Cn + y Cn + z VDD = 16 VSS = 8 |
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Mô tả tương tự - CD40182BMS |
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