7-53

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

CD4011BMS, CD4012BMS

CD4023BMS

CMOS NAND Gates

Pinouts

CD4011BMS

TOP VIEW

CD4012BMS

TOP VIEW

CD4023BMS

TOP VIEW

A

B

J = AB

K = CD

C

D

VSS

VDD

H

G

M = GH

L = EF

E

F

1

2

3

4

5

6

7

14

13

12

11

10

9

8

J = ABCD

A

B

C

D

NC

VSS

VDD

K = EFGH

H

G

F

E

NC

1

2

3

4

5

6

7

14

13

12

11

10

9

8

NC = NO CONNECTION

A

B

D

E

F

K = DEF

VSS

VDD

G

H

I

L = GHI

J = ABC

C

1

2

3

4

5

6

7

14

13

12

11

10

9

8

Features

• High-Voltage Types (20V Rating)

• Propagation Delay Time = 60ns (typ.) at CL = 50pF,

VDD = 10V

• Buffered Inputs and Outputs

• Standardized Symmetrical Output Characteristics

• Maximum Input Current of 1

µA at 18V Over Full Package-

• 100% Tested for Maximum Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Noise Margin (Over Full Package Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Stan-

dards No. 13B, “Standard Specifications for Descrip-

tion of “B” Series CMOS Device’s

Description

CD4011BMS, CD4012BMS, and CD4023BMS NAND gates

provide the system designer with direct implementation of

the NAND function and supplement the existing family of

CMOS gates. All inputs and outputs are buffered.

The CD4011BMS, CD4012BMS and the CD4023BMS is

supplied in these 14 lead outline packages:

CD4011BMS - Quad 2 Input

CD4012BMS - Dual 4 Input

CD4023BMS - Triple 3 Input

CD4011B

CD4012B

CD4023B

Braze Seal DIP

H4Q

H4H

H4Q

Frit Seal DIP

H1B

H1B

H1B

Ceramic Flatpack

H3W

H3W

H3W

File Number

3079

November 1994