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CD4007 bảng dữ liệu(PDF) 1 Page - Intersil Corporation |
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CD4007 bảng dữ liệu(HTML) 1 Page - Intersil Corporation |
1 / 9 page 7-666 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CD4007UBMS CMOS Dual Complementary Pair Plus Inverter Pinout CD4007UBMS TOP VIEW Functional Diagram Q2 (P) DRAIN Q2 (P) SOURCE Q2 GATES Q2 (N) SOURCE Q2 (N) DRAIN Q1 GATES VDD, Q1, Q2, Q3 (P) Q1 (P) SOURCE Q3 (N) DRAIN, Q3 (P) SOURCE Q3 (P) DRAIN Q3 GATES Q3 (N) SOURCE Q1 (N) DRAIN 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VSS, Q1, Q2, Q3 (N) SUBSTRATES Q1 (N) SOURCE SUBSTRATES, Q1(P) DRAIN 6 TERMINAL NO. 14 - VDD TERMINAL NO. 7 - VSS p n p n p n 12 310 74 9 13 1 5 8 14 2 11 Features • High-Voltage Type (20V Rating) • Standardized Symmetrical Output Characteristics • Medium Speed Operation - tPHL, tPLH = 30 ns (typ) at 10V • 100% Tested for Maximum Quiescent Current at 20V • Meets All Requirements of JEDEC Tentative Stan- dards No. 13B, “Standard Specifications for Descrip- tion of “B” Series CMOS Devices” • Maximum Input Current of 1 µA at 18V Over Full Pack- age-Temperature Range; 100nA at 18V and +25oC Applications • Extremely High-Input Impedance Amplifiers • Shapers • Inverters • Threshold Detector • Linear Amplifiers • Crystal Oscillators Description CD4007BMS types are comprised of three n-channel and three p-channel enhancement-type MOS transistors. The transistor elements are accessible through the package ter- minals to provide a convenient means for constructing the various typical circuits as shown in Figure 2. More complex functions are possible using multiple pack- ages. Numbers shown in parentheses indicate terminals that are connected together to form the various configurations listed. The CD4007BMS is supplied in these 14 lead outline pack- ages: Braze Seal DIP H4Q Frit Seal DIP H1B Ceramic Flatpack H3W November 1994 File Number 3291 |
Số phần tương tự - CD4007 |
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Mô tả tương tự - CD4007 |
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