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LM555CN bảng dữ liệu(PDF) 3 Page - Intersil Corporation

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Giải thích chi tiết về linh kiện  Timers for Timing Delays and Oscillator Applications in Commercial, Industrial and Military Equipment
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3
Schematic Diagram
Typical Applications
Reset Timer (Monostable Operation)
Figure 1 shows the CA555 connected as a reset timer. In this
mode of operation capacitor CT is initially held discharged by
a transistor on the integrated circuit. Upon closing the “start”
switch, or applying a negative trigger pulse to terminal 2, the
integral timer flip-flop is “set” and releases the short circuit
across CT which drives the output voltage “high” (relay
energized). The action allows the voltage across the capacitor
to increase exponentially with the constant t = R1CT. When
the voltage across the capacitor equals 2/3 V+, the
comparator resets the flip-flop which in turn discharges the
capacitor rapidly and drives the output to its low state.
Since the charge rate and threshold level of the comparator
are both directly proportional to V+, the timing interval is
relatively independent of supply voltage variations. Typically,
the timing varies only 0.05% for a 1V change in V+.
Applying a negative pulse simultaneously to the reset
terminal (4) and the trigger terminal (2) during the timing
cycle discharges CT and causes the timing cycle to restart.
Momentarily closing only the reset switch during the timing
interval discharges CT, but the timing cycle does not restart.
6
THRESHOLD
7
RESET
DISCHARGE
V-
RESET
DISCHARGE
3
OUTPUT
OUTPUT
FLIP-FLOP
TRIGGER
COMPARATOR
THRESHOLD
COMPARATOR
4.7K
830
4.7K
D2
D1
Q3
Q4
Q7
Q5
Q2
Q1
10K
Q8
Q6
100
100K
Q9
Q11 Q12
1K
Q10
5K
Q13
Q16
7K
D3
Q14
Q15
Q17
3.9K
Q19
Q20
Q21
Q18
8
V+
CONTROL
VOLTAGE
5K
6.8K
5K
4.7K
220
4.7K
5
2
4
1
TRIGGER
D4
NOTE: Resistance values are in ohms.
1
CA555
EO
8
5
2
6
7
3
4
680
RESET
R1
CT
4.7K
680
10K
0.01
µF
RELAY
COIL
1N4001
V+
5V
S1
START
NOTE: All resistance values are in ohms.
FIGURE 1. RESET TIMER (MONOSTABLE OPERATION)
CA555, CA555C, LM555C


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